Given the architecture on the previous page. you are to write the micro operatio

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Given the architecture on the previous page. you are to write the micro operations for the "macro-operations that are specified below, Note: all the control signals (LIys, OEs, ALU Op. MUX Selects, etc.) would came file contki 6 registers, nam ed R0 h being 32-bi ide, You can during one clock cycle. The R output will have the con ofthe register addressed by the R Addr inputs, and the s output will have the contents of the register addressed by the S Addr inputs. You write to one of the registers by having the data to be written availahle on the w inputs and the address or the register lo be written W Add puts. The register file kan be wriue being read. Note the RD and WR control signals of the register file would have lo be asserted appropriately for proper operation. The Memory Module has a common data parh for reading and writing. Thus, yau may inly read or write to memory durins one clock cycle. The address of the memory register to be written lo, or read frum, must be placed in the address register (MAR) on a clock cycle prior rhe clock cycle in which you access the memory module. Data to be written to memory must be put in the WrBuf to the clock kyrie in which you write to prior memory, Data to be read from memory will go into RdBuf, and will be available in the newl lock cycle. ons defined for the ALU the table below Op You are to write the RTL for the micro-operations necessary to execute the following macro-operations. These are not concurrent operations, but are to be done in sequence, one after another R15 R l) add R15. R2, R3 MDR xct R7, R7, 1) inc R3+R 5) mov IR15], DR14+R lj #MIRIS) R14 R13 ij R. sub R 4 R7, R3 Note: None of the general registers (RO R15) are to he destroyed unless they are a deslinalion register. All ather registers (aside from memory registers are considered lo be "scrntch registers' lo bold inlermediate values for the execution of the macro-operatiats Sci

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