1. Ripple-Carry Adder RCA) First write a module for a full adder (FA) with: Inpu
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1. Ripple-Carry Adder RCA) First write a module for a full adder (FA) with: Inputs: x, y and cin (all 1 bit). outputs: s and cout (both 1 bit). Use Figs. 3.4 and 3.18, 3.19, 3.20 or 3.21 for implementation details. To represent realistic hardware, we will assume that each gate has a delay of 1ns. A portion of the Verilog code for the FA in this case is shown below: timescale 1ns/10ps module FA delay (x, y, cin, s, cout) input x, y, cin output s Cout wire a xor #1 X1 (a, x, y) 1 time unit (1 ns) delay Add the rest of the code here endmodule Use the FA delay module to build a 32-bit ripple-carry adder (RCA) according to Fig. 3.5. The module RCA consists of 32 instances of FA delay and has Inputs: 32-bit vectors x and Y, 1-bit cin. Outputs: 32-bit vector s and 1-bit cout. HINT: You will find the Verilog generate statement very useful. See section 3.5.4.Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;
architecture Behavioral of full_adder_vhdl_code is
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Testbench_full_adder IS
END Testbench_full_adder;
ARCHITECTURE behavior OF Testbench_full_adder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT full_adder_vhdl_code
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
S : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic;
signal Cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: full_adder_vhdl_code PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
A <= '1';
B <= '0';
Cin <= '0';
wait for 10 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 10 ns;
A <= '1';
B <= '1';
Cin <= '0';
wait for 10 ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 10 ns;
A <= '1';
B <= '0';
Cin <= '1';
wait for 10 ns;
A <= '0';
B <= '1';
Cin <= '1';
wait for 10 ns;
A <= '1';
B <= '1';
Cin <= '1';
wait for 10 ns;
end process;
END;
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