Using the above figure implement a six bit multiplier in VHDL, i.e. Multiplicand

Question

Using the above figure implement a six bit multiplier in VHDL, i.e. Multiplicand register contain 6

bits, Product register contain 12 bits. The ALU unit can be 6-

bit adder (behavioral code).

You need to write a control circuit that does following:

a.

Loads the value into register, checks the LSB of multiplier and correspondingly

adds the bits or generates all 0s for the upper half of Produc

t register.

b.

Next it updates the Product register and shift one bit to the right

c.

Control unit is also responsible to stop the multiplication operation and store the

final value in a separate register (not shown in the figure).

2)

Write a test

-bench to perfor

m 3 multiplication operations. First of which should have all

‘0’ values for the multiplier.

Explanation / Answer

Here I am explaining the details of a 6 bit multiplier.

This multiplier is used to multiply two 6 but datas.

The sample code is give below

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity SIXBitMultiplier is

    Port ( C: in STD_LOGIC_VECTOR (3 downto 0);

           D: in STD_LOGIC_VECTOR (3 downto 0);

           Result : out STD_LOGIC_VECTOR (7 downto 0));

end SIXBitMultiplier;

architecture Dataflow of SIXBitMultiplier is

begin

Result <= std_logic_vector(unsigned(C) * unsigned(D));

end Dataflow;

VHDL Test Bench for 6-Bit Multiplier:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY TestSIXBitMultiplier IS

END TestSIXBitMultiplier;

ARCHITECTURE behavior OF TestSIXBitMultiplier IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT SIXBitMultiplier

    PORT(

         C: IN std_logic_vector(3 downto 0);

         D : IN std_logic_vector(3 downto 0);

         Result : OUT std_logic_vector(7 downto 0)

        );

    END COMPONENT;

   --Inputs

   signal C : std_logic_vector(3 downto 0) := (others => '0');

   signal D : std_logic_vector(3 downto 0) := (others => '0');

    --Outputs

   signal Result : std_logic_vector(7 downto 0);

   -- No clocks detected in port list. Replace below with

   -- appropriate port name

   constant clock_period : time := 10 ns;

BEGIN

   uut: FourBitMultiplier PORT MAP (

          C=> C,

          D => D,

          Result => Result

        );

stim_proc: process

   begin      

      -- hold reset state for 100 ns.

      wait for 100 ns;

        C <= "000000";

        D <= "101010";

        wait for clock_period*10;

        C <= "111111";

        D <= "101010";

        wait for clock_period*10;

        C <= "1111";

        D <= "1111";

      wait;

   end process;

END;

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