Interrupts in the ARM v7-M are handled by the Nested Vectored Interrupt Controll

Question

Interrupts in the ARM v7-M are handled by the Nested Vectored Interrupt Controller (NVIC). The NVIC has two functions, to enable interrupts and to assign priority to interrupts. Up to how many interrupt sources can the NVIC support? How can the software determine how many external interrupt lines are supported by a particular implementation? Where does the interrupt vector table reside in the memory layout of a Cortex-M4 microcontroller? How can the priority of interrupts be changed? How can the software support multiple interrupt vector tables?

Explanation / Answer

The NVIC supports upto 496 interrupted. And for the ARM cortex-M architecture the interrupts are depend upon the silicon designer and the chip integrated.

In NVIC there is a register called general interrupt controller type register (ICTR) which contains all the informationabout the interrupts, the software will know the interrupts information from this register.

Interrupt vector table is located at the memory location 0x00 in the cortex m4 microcontroller.

The priority of interrupts can be changed through the priority level registers. Before changing priorities we need to deactivate the priority first otherwise the result will be unpredictable. However in cortex m3 and m4 microcontrollers the priorities will be changed dynamically. No need to change manually.

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