For the following questions, assume that the memory system uses byte addressable
ID: 3812688 • Letter: F
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For the following questions, assume that the memory system uses byte addressable that are 32-bit long. In addition, assume all data words in such memory consists of 4-bytes (32-bits). Answer the following questions: Design a 4-way set associative cache that can store 1 M byte of data. Assume each cache block consist of 8 data words. Make sure to indicate the total number of cache sets, size of tag/data field, and which part of the address is used as tag and cache set selection. In addition, show all wirings needed to identify the hits and the section of appropriate set/word in the cache. What is the total number of bits needed to implement the cache if it has valid and dirty bit fields? Show your work. Given the following memory byte addresses, identify whether it is a hit or a miss assuming an initially empty cache: 0D (00000000H), 671090688D (28000800H), 24D (00000018H), 671088664D (28000018H), 13421774D (28000040H) Assume the cache uses an LRU replacement algorithm. In addition, show the final content of cache for the given address sequence.Explanation / Answer
Given, Main memory is byte addressable and
Length of Main Memory address is = 32 bits
Toal Main Memory Size is = 232 bytes = 4 GB
Length of Data Word is = 4B
(1.1)
Given Size of Cache is = 1 MB
Size of cache block is = 8 Words = 8 * 4B = 32B
Total number of cache blocks is = Size of Cache / Size of cache block
= 1 MB / 32B
= 220 / 25
= 215
Hence Total number of cache blocks is = 215.
Given that cache is 4-way set associative so in one set we will have 4 blocks.
Hence Total number of sets is = 215 / 4 = 213.
Here the number of bits needed to address a set is = set offset = log2 213 = 13 bits.
Number of bits needed to address a word in a block is = word offset = log2 23 = 3 bits.
Number of bits needed for TAG is = log2 M/S
where M is = Total Number of Main Memory Blocks = 232 B / 25 B = 227
N is = Total Number of cache Memory sets = 213
Hence number of bits for TAG is = log2 227 / 213 = log2 214 = 14 bits.
(1.2)
Total Number of bits to address cache is = TAG + Set offset + Word offset
= 14 + 13 +3
= 30 bits
If we add 2 bits for valid and dirty fields then
Total Number of bits to address cache is = 30 + 2 = 32 bits.
(1.3)
00000000H is the 1st memory reference and as cache is empty it is a miss
and it will place in 0th block of 0th set in the cache.
28000800H is the 2nd reference and in binary it is as below
0010 1000 0000 0000 0000 1000 0000 0000
Here TAG + Dirty + valid is first 16 bits which is = 0010 1000 0000 0000
Set offset is next 13 bits which is = 0000 1000 0000 0 = 256th set
Hence this is also a miss.
00000018H is the 3rd reference and in binary it is as below
0000 0000 0000 0000 0000 0000 0001 1000
Here TAG + Dirty + valid is first 16 bits which is = 0000 0000 0000 0000
Set offset is next 13 bits which is = 0000 0000 0001 1 = 3rd set.
Hence this is also a miss.
28000018H is the 4th reference and in binary it is as below
0010 1000 0000 0000 0000 0000 0001 1000
Here TAG + Dirty + valid is first 16 bits which is = 0010 1000 0000 0000
Set offset is next 13 bits which is = 0000 0000 0001 1 = 3rd set.
Hence this is also a miss.
28000040H is the 5th reference and in binary it is as below
0010 1000 0000 0000 0000 0000 0100 0000
Here TAG + Dirty + valid is first 16 bits which is = 0010 1000 0000 0000
Set offset is next 13 bits which is = 0000 0000 0100 0 = 8th set.
Hence this is also a miss.
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