What would the status of the down counter\'s six output bits (i.e. bits A, B, C,
ID: 3812328 • Letter: W
Question
What would the status of the down counter's six output bits (i.e. bits A, B, C, D, E and F) of the 6 stage ripple down counter be after clock pulses 1 - 10?? (assume the counter is reset to 0000 at time 0, just before clock pulse 1) Note output A is least significant bit. For a 5 bit parallel up counter circuit, (similar to parallel counter in Fig 10-6) determine the status of output bits A - E for the corresponding clock pulses. Assume the counter was reset to 00000 just before clock pulse 1 is applied.Explanation / Answer
d)
A down counter will counts from higher number to lower number, for suppose if we have a
2 bit down counter and if the starting state if 00 then it wont go to 01 instead it will go to
11 in the same way it will count as follow
00 ----> 11 -----> 10 -----> 01 -----> 00 (0 ----> 3 -----> 2 -----> 1 -----> 0)
In the same way for 6 bits it will go to 63 from 0 and then from 63 to 54
in 10 clock pulses it will go as below,
CLK A B C D E F
0 0 0 0 0 0 0
1 1 1 1 1 1 1
2 0 1 1 1 1 1
3 1 0 1 1 1 1
4 0 0 1 1 1 1
5 1 1 0 1 1 1
6 0 1 0 1 1 1
7 1 0 0 1 1 1
8 0 0 0 1 1 1
9 1 1 1 0 1 1
10 0 1 1 0 1 1
e)
An up counter will counts from lower number to higher number, for suppose if we have a
2 bit down counter and if the starting state if 00 then it will go to 01 and to
10 in the samw way it will count as follow
00 ----> 01 -----> 10 -----> 11 -----> 00 (0 ----> 1 -----> 2 -----> 3 -----> 0)
In the same way for 5 bits it will count from 0 to 8 in 8 clock pulses
CLK A B C D E
0 0 0 0 0 0
1 0 0 0 0 1
2 0 0 0 1 0
3 0 0 0 1 1
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0
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