Advanced Computer Architecture 510/610 Winter 2016 This question will be about t

Question

Advanced Computer Architecture 510/610 Winter 2016 This question will be about the following computer: 1.5 GHz, No Pipeline, instruction buffers that negate instruction load penalties 32Kb L1 cache, 1 cycle access, 4-way associative, write-through, not write-allocate, 2% miss rate for Data and a miss rate of 1% for Instructions 1Mb L2 cache, 3 cycle access, 4-way associative, write-back, 30% miss rate, 20% dirty Block size is 4 32-bit words for both caches 1Gb RAM, DDR2 1.5 GHz 20 nanosecond latency 2-bit dynamic branch predictor that is right 90% of the time. When the prediction is correct and it is a branch not taken then there is no penalty. When the prediction is to branch and it is correct, there is a 1 cycle penalty, and there is a 2 cycle penalty if incorrect. Assume branches are 1/5 of all instructions, 4/5 of branches are taken, memory access is 1/10 of all instructions. What is CPI?

Explanation / Answer

Hello ,

Please find the answer to question below:-

I have mentioned the formula to calculate CPI for two level caches and also taken assumptions wherever necessary:-

Effective CPI=Base CPI+ (misratel1*misspenaltyl2)+(global miss rate*miss penalty l1)

Assumed that base cpi = 1;

miss rate l1=0.02(data)+0.01(instruction)=0.03
miss rate l2=0.3(overall)
global miss rate=miss rate l1+miss aret l2=0.03+.3=0.06
memory access time=20 nanosecond(latency)
miss penalty for l1 20/0.03=666.6
miss penalty for l2 =20/0.3=66.6

CPI = 1+(0.03*66.6) +(0.06*666.6)
=1+1.99+39.996
=42.986

Related Questions

Navigate

• Browse (All)
• Browse A
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.