A characteristic of the ARM architecture is its predicated execution model. Inst

Question

A characteristic of the ARM architecture is its predicated execution model. Instructions can be conditionally executed depending on the status flags on the CPU. For example, store can be conditionally executed by predicating the instruction with the It suffix: strlt r2, [r0], #4. Predicated execution is not readily available in the Cortex-M series. For this purpose, the ARM v7-M architecture defines the it instruction. Describe the functionality of this instruction. Utilize this instruction to write a small routine that clears the. bss segment of a program. You may assume that the start address of the .bss segment is at __bss_start__ and the end address at _bss_end __.

Explanation / Answer

IT instruction allows the conditional execution of instruction. It specifies a block of up to four instructions.

Following is the syntax.

IT{x}{y}{z}            {cond}

x is the condition switch for 2nd instruction in the block

y is the condition switch for 3rd instruction in the block

z is the condition switch for 4th instruction in the block

{cond} is one of the following

0000 = EQ - Z set (equal)

0001 = NE - Z clear (not equal)

0010 = HS / CS - C set (unsigned higher or same)

0011 = LO / CC - C clear (unsigned lower)

0100 = MI -N set (negative)

0101 = PL - N clear (positive or zero)

0110 = VS - V set (overflow)

0111 = VC - V clear (no overflow)

1000 = HI - C set and Z clear (unsigned higher)

1001 = LS - C clear or Z (set unsigned lower or same)

1010 = GE - N set and V set, or N clear and V clear (>or =)

1011 = LT - N set and V clear, or N clear and V set (>)

1100 = GT - Z clear, and either N set and V set, or N clear and V set (>)

1101 = LE - Z set, or N set and V clear,or N clear and V set

1110 = AL - always

1111 = NV - reserved.

Condition switch could be either T (Then) or E (else).

If it is T, then instruction is executed if condition is True.

If it is E, then instruction is executed if condition is not true.

For 1st instruction, condition switch is always T.

Also Note that all instructions (except BKPT ) in IT Block must specify {cond} in their syntax.

For example

/*Incorrcect*/

IT            HI

ADD       r1,r1,#5

/*Correct*/

ITE          EQ

SUBEQS                                r1,r1,#1

ADDNES               r2,r2,#5

ADDNE                 r3,r3,#1

Some of the restrictions in the IT block are:

Assembl y Program to clear . bss segment.

AREA     Program,CODE,READONLY

ENTRY

Main     move    r0,#0      ;move 0 into register r0

                Ldr          r1,=_sbss             ;load r1 with starting address of sram bss

                Ldr          r2,=_ebss            ;load r2 with ending address of sram bss

LOOP     ITET        EQ                          ;It instruction with condition code equal (if zero flag is set)

                cmpEQ r1,r2                       ;compare r1 with r2

                StrLO     r0,[r1],#4             ;if r1 < r2 ,store the value of r0(0) into mem location pointed by r1 and ;increment r1 to point to next location.

blLO       LOOP

AREA     bss,DATA,NOINIT

Store     %            20

                END

Please let me know for any doubts.

Thanks.                  

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