I am trying to display the 7 segment display in verilog for sec on the altera bo

Question

I am trying to display the 7 segment display in verilog for sec on the altera board but it is giving me an error "left-hand side of assignment must have a variable data type" for sec.

sec is just seconds

module clocktimer #(parameter ssize 7 parameter Hsize-6) (output CSsize setmin, output [Hsize Sec, min wire csec,cmin,chr CSet clockN (Ssize) Seconds (sec 59 clk,reset,1) clockN (Ssize) Minutes (min Cmi 59 Csec ,reset ,1) clockN #(Hsize) Hours Chr hr 23 min,reset,1) cl kcnt1 setminutes (clk, reset adjust, minadj, setmin); clkcnt2 sethours CC1k,reset, adjust,hour adj,Sethr); always begi case(clk) 5 b00000 7 b1000000 Sec 5 b00000 7 b1111001 Sec 5 'b00000 7 b0100100 Sec 5 'b00000 Sec 7 b01100000 5 b00000 Sec 7 b0011001 5 b00000 Sec 7 b0010010 5 'b00000 7 b0000010 Sec 5 'b00000 Sec 7 b1111000 5 b00000 7 b0000000 Sec 5 'b00000 Sec 7 b0011000 encase end endmodule hr sethr input clk,reset,adjust

Explanation / Answer

You cannot make a procedural assignment to a wire. You must make a procedural assignment to a reg. Basically, always blocks cannot assign to wires, only regs. assign statements on the other hand, assign to wires not regs.

So

1) declare sec as: output reg sec

OR

2) reg [1:0] rsec;

DO THUMBS UP ^_^

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