Name: ______________ EEEE-220 – HW14 – Check on mycourses for the due date and t
ID: 3807537 • Letter: N
Question
Name: ______________
EEEE-220 – HW14 – Check on mycourses for the due date and time.
Type and show the complete VHDL code for a 16-to-1 multiplexer implemented with 5 4-to-1 multiplexers and using the FOR and IF GENERATE statements. Follow the example in module 15. This is structural code description, so if it helps to visualize it, re-draw the schematic of a 16-to-1 multiplexers implemented using 5 4-to-1 multiplexers. The latter is considered an available component. You can download this *.doc file and type your code below.
Explanation / Answer
1 LIBRARY ieee ;
2 USE ieee.std_logic_1164.all ;
3 LIBRARY work ;
4 USE work.mux4to1_package.all ;
5 ENTITY mux16to1 IS
6 PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
7 s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
8 f : OUT STD_LOGIC ) ;
9 END mux16to1 ;
10 ARCHITECTURE Structure OF mux16to1 IS
11 SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
12 BEGIN
13 Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;
14 Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
15 Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;
16 Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;
17 Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
18 END Structure
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