library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all ; entity mo
ID: 3804990 • Letter: L
Question
library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all ; entity mod9CounterC is port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(3 downto 0) ); end entity; architecture behavioral of mod9CounterC is -- -- internal signals -- signal state: unsigned(3 downto 0); signal state_next : unsigned(3 downto 0); begin -- -- next state logic -- with state select state_next <= "0001" when "0000", "0010" when "0001", "0011" when "0010", "0100" when "0011", "0101" when "0100", "0110" when "0101", "0111" when "0110", "1000" when "0111", "1001" when "1000", "0000" when others; -- -- Register logic -- process(clk, rstb ) begin -- reset if (rstb = '0') then state <= (others => '0'); -- rising clk edge elsif (rising_edge (clk)) then state <= state_next ; end if; end process; -- -- Output logic -- bout <= std_logic_vector(state); end behavioral;
1 Modify the mod9 counter from the notes to be a mod9 or mod5 counter. Assume there is an additional input called mode (mode-0 mod5, mode-1 mod9). Provide your code and a simulation clearly showing the 2 modes and wrap- 20pts aroundExplanation / Answer
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity mod9CounterC is
port ( clk : in std_logic;
rstb : in std_logic;
bout : out std_logic_vector(3 downto 0)
);
end entity;
architecture behavioral of mod9CounterC is
signal state:
unsigned(3 downto 0);
signal state_next :
unsigned(3 downto 0);
begin
with state select state_next <= "0001"
when "0000", "0010"
when "0001", "0011"
when "0010", "0100"
when "0011", "0101"
when "0100", "0110"
when "0101", "0111"
when "0110", "1000"
when "0111", "1001"
when "1000", "0000"
when others;
process(clk, rstb )
begin
-- reset
if (rstb = '0') then state <= (others => '0');
-- rising clk edge
elsif
(rising_edge (clk)) then state <= state_next ;
end if;
end process;
bout <= std_logic_vector(state);
end behavioral;
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