In VHDL language we can describe a variable-size counter by using a generic decl
ID: 3803822 • Letter: I
Question
In VHDL language we can describe a variable-size counter by using a generic declaration. A example of an n-bit counter is shown as follows library feee: use ieee.std_logic_1164.all: use ieee.std_logic_arith.all: use ieee.std_logic_signed.all: entity counter is generic (n: natural: - 4:): port (clock: in STD_LOGIC: reset_n: in STD_LOGIC: 0: out STD_LOGIC_VECTOR (n-1 downto 0)): end entity: arthitecture rt1 of counter is signal value: std_logic_vector(n-1 downto 0): begin PROCESS (clock.reset_n) begin if (result_n - '0') then value leftarrow (OTHERS rightarrow '0'): elsif ((clock event) and (clock = '1')) then value leftarrow value + 1: end if: end process: 0 leftarrow value: end rt1: The parameter in specifies the number of bits in the counter. A particular value of this parameter is defined by using a generic map statement. For example, an 8-bit counter can be specified as: eight_bit:counter generic map (n rightarrow 8) port map eight_bit(clock. rset_n.0): By using parameters we can instantiate counters of different sizes in a logic circuit, without having to create a new module for each counter. Create a modulo-k counter by modifying the design of an 8-bit counter to contain an additional parameter. The counter should count from 0 to k - 1. When the counter reaches the value k - 1 the value that follows should be 0. Your circuit should use pushbutton KEY0 as an asynchronous reset, KEY 1 as a manual clock input. The contents of the counter should be displayed on red LEDs. Compile your design with Quartus II software, download your design onto a DE1 board, and test its operation. Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2-0. Derive a control signal, from the 50-MHz clock signal provided on the DE1 board, to increment the contents of the counter at one-second intervals. use the pushbutton switch KEY0 to reset the counter 10 0.Explanation / Answer
below is the VHDl code for part 2 question asked
BCounter.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
-- 3-digit BCD counter.
ENTITY BCounter IS
PORT ( CLOCK_50 : IN STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H3, H2, H1, H0 : OUT STD_LOGIC_VECTOR(0 TO 6));
END BCounter;
ARCHITECTURE Behavior OF BCounter IS
COMPONENT BCD7segment
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
SIGNAL slow_count : STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL BCD0, BCD1, BCD2: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
--to create a 1Hz 4-bit counter
-- First, a counter to produce a 1 second (approx) enable
PROCESS (CLOCK_50)
BEGIN
IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
slow_count <= slow_count + '1';
END IF;
END PROCESS;
-- 3-digit BCD counter that uses a slow enable
PROCESS (CLOCK_50)
BEGIN
IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
IF (KEY(3) = '0') THEN
BCD0 <= "0000";
BCD1 <= "0000";
BCD2<= "0000";
ELSIF (slow_count = 0) THEN
IF (BCD0 = "1001") THEN
BCD0 <= "0000";
IF (BCD1 = "1001") THEN
BCD1 <= "0000";
IF (BCD2= "1001") THEN
BCD2<= "0000";
ELSE
BCD2<= BCD2+ '1';
END IF;
ELSE
BCD1 <= BCD1 + '1';
END IF;
ELSE
BCD0 <= BCD0 + '1';
END IF;
END IF;
END IF;
END PROCESS;
-- to drive a 7 segment displays
digit2: BCD7segment PORT MAP (bcd_2, H2);
digit1: BCD7segment PORT MAP (BCD1, H1);
digit0: BCD7segment PORT MAP (BCD0, H0);
-- to blank the adjacent displays
digit3: BCD7segment PORT MAP ("1111", H3);
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY BCD7segment IS
PORT ( bcdDisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
display : OUT STD_LOGIC_VECTOR(0 TO 6));
END BCD7segment;
ARCHITECTURE Behavior OF BCD7segment IS
BEGIN
-- this is the display structure
-- 0
-- ---
-- | |
-- 5| |1
-- | 6 |
-- ---
-- | |
-- 4| |2
-- | |
-- ---
-- 3
--
PROCESS (bcdDisp)
BEGIN
CASE bcdDisp IS
WHEN "0000" => display <= "0000001";
WHEN "0001" => display <= "1001111";
WHEN "0010" => display <= "0010010";
WHEN "0011" => display <= "0000110";
WHEN "0100" => display <= "1001100";
WHEN "0101" => display <= "0100100";
WHEN "0110" => display <= "1100000";
WHEN "0111" => display <= "0001111";
WHEN "1000" => display <= "0000000";
WHEN "1001" => display <= "0001100";
WHEN OTHERS => display <= "1111111";
END CASE;
END PROCESS;
END Behavior;
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