Let TS be the average time to access an item in memory. Let T1 be the time to ac

Question

Let TS be the average time to access an item in memory.

Let T1 be the time to access an item in level 1 cache

Let T2 be the time to access an item in level 2 cache

Let TM be the time to access an item in main memory

Let H1 be the hit rate for level 1 cache.

Let M2 be the miss rate for level 2 cache.

Also consider that the average memory access time per instruction is AMAT = Time for a hit x Miss rate x Miss penalty

Assume you have a 4 GHz CPU with a CPI of 1.0 (instructions on this CPU require 1.0 cycles per instruction on average) and a main memory access time of 100 ns. How many clock cycles are required for a main memory access?

Explanation / Answer

Given Frequency of the CPU is 4 GHz

We know that Clock Period = 1 / frequency secs

= 1 / (4 * 109) secs

= (1 / 4 ) * 10-9 secs

= 0.25 nsecs (nano secs)

we know that, Total time = number of clocks * clock period

   Main Memory access time = number of clocks for a main memory access * clock period

Given Main Memory access time = 100 ns and we caluculated Clock Period = 0.25 ns

So Number of clocks for a main memory access = Main Memory access time / clock period

   = 100/0.25

   = 400

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