I do not understand why the base address of page tables and page frames can be e
ID: 3801291 • Letter: I
Question
I do not understand why the base address of page tables and page frames can be extended from 20 to 24 bits. Can anyone explain how to do the calculation? Thank you.
software developers began to discover the memory limitations software memo of architectures, Intel adopted a page address extension (PAE, which allows 32-bit processors to access a physical address space larger than 4GB. The fundamental difference in by PAE support was that paging went from a two-level scheme (as shown in Figure 8.23) to a three-level scheme, where the top two bits refer to a page directory pointer table. Figure 8 illustrates a PAE system with 4-KB pages. (PAE also supports 2-MB pages.) page directory page table 12 11 3130 29 21 20 4-KB page CR3 register page directory page page pointer table directory table Figure 8.24 Page address extensions.Explanation / Answer
Every page entry gets the address of physical memmory.If we consider single level of paging ,the resulting page table contains entries for all the pages of virtual address space,then we can say
Number of entries in page table = size of virtual address space / page size .
As per above formula,there will be 2(32-12) = 220entries.
Therefore the number of bits required to address 64MB physical memmory =26bits.
Number of Page frames in physical memory is 2(26-12) = 214.
Hence each page table entry will contain 14 bits address of the page frames and there will be 1 bit to tell valid or invalid.SInce the memory is byte addressable,each page entry is 16 bits .ie., 2 bytes long.
Size of Page table = Total number of page table entries * size of page table entries
Which will be equal to 220*2 =2MB
PAE is activated by setting the Physical Address Extension (PAE) flag in the cr4 control register. The Page Size (PS) flag in the page directory entry enables large page sizes (2 MB when PAE is enabled).
The entries of Page Directories and Page Tables have the following structure:
Page Frame physical Address(20 bits)
Avail
G
PS
D
A
PCD
PWT
U/S
R/W
P
31 12
20 bits
11 9
3 bits
8
1bit
7
1bit
6
1bit
5
1bit
4
1bit
3
1bit
2
1bit
1
1bit
0
1bit
As per above structure, PAE Page Table entry must include the 12 flag bits (32 - 20 (Field) = 12 and the 24 physical address bits, for a total of 36 bits, so the Page Table entry size has been doubled from 32 bits to 64 bits. As a result, a 4-KB PAE Page Table includes 512 entries instead of 1,024.
Once cr3 is set, it is possible to address up to 4 GB of RAM. If we want to address more RAM, we'll have to put a new value in cr3 or change the content of the PDPT.
However, the main problem with PAE is that linear addresses are still 32 bits long. This forces kernel programmers to reuse the same linear addresses to map different areas of RAM.
Page Frame physical Address(20 bits)
Avail
G
PS
D
A
PCD
PWT
U/S
R/W
P
31 12
20 bits
11 9
3 bits
8
1bit
7
1bit
6
1bit
5
1bit
4
1bit
3
1bit
2
1bit
1
1bit
0
1bit
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