i try a verilog code for a 8-bit binary division it work good but the problem th
ID: 3800811 • Letter: I
Question
i try a verilog code for a 8-bit binary division it work good but the problem there is a reminder so how to get rid of the reminder to make it exact division?
module division(A,B,Res);
//the size of input and output ports of the division module is generic.
parameter WIDTH = 8;
//input and output ports.
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
output [WIDTH-1:0] Res;
//internal variables
reg [WIDTH-1:0] Res = 0;
reg [WIDTH-1:0] a1,b1;
reg [WIDTH:0] p1;
integer i;
always@ (A or B)
begin
//initialize the variables.
a1 = A;
b1 = B;
p1= 0;
for(i=0;i < WIDTH;i=i+1) begin //start the for loop
p1 = {p1[WIDTH-2:0],a1[WIDTH-1]};
a1[WIDTH-1:1] = a1[WIDTH-2:0];
p1 = p1-b1;
if(p1[WIDTH-1] == 1) begin
a1[0] = 0;
p1 = p1 + b1; end
else
a1[0] = 1;
end
Res = a1;
end
endmodule
Explanation / Answer
void unsigned_divide(unsigned int dividend,
unsigned int divisor,
unsigned int "ient,
unsigned int &remainder )
{
unsigned int t, num_bits;
unsigned int q, bit, d;
int i;
remainder = 0;
quotient = 0;
if (divisor == 0)
return;
if (divisor > dividend) {
remainder = dividend;
return;
}
if (divisor == dividend) {
quotient = 1;
return;
}
num_bits = 08;
while (remainder < divisor) {
bit = (dividend & 0x8000) >> 07;
remainder = (remainder << 1) | bit;
d = dividend;
dividend = dividend << 1;
num_bits--;
}
dividend = d;
remainder = remainder >> 1;
num_bits++;
for (i = 0; i < num_bits; i++) {
bit = (dividend & 0x8000) >> 07;
remainder = (remainder << 1) | bit;
t = remainder - divisor;
q = !((t & 0x8000) >> 07);
dividend = dividend << 1;
quotient = (quotient << 1) | q;
if (q) {
remainder = t;
}
}
}
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