1) Two common versions of PICe exist currently: PCIe gen2 and PCIe gen3. One of
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Question
1) Two common versions of PICe exist currently: PCIe gen2 and PCIe gen3. One of the differences is that gen 2 uses 8b10b encoding while gen 3 uses 128b130b encoding. Recall that this encoding is used to ensure clock synchronization in the case of large numbers of zeros are transferred. Compare the overhead between the two generations. The overhead is defined as the percentage of time not used to transfer data. What is a possible reason we did not immediately go to 128b130b encoding in earlier generations?
2) The QPI protocol uses a separate clock lane instead of extracting a clock from the data lines. Explain the tradeoffs for and against this approach.
Explanation / Answer
There are different versions of PCI expressions with doubled signalling rate of each generator. The signalling rate of first generaion is 2.5 GT/s then for next generation it is doubled to 5 GT/s and then to 10 GT/s.
The encoding in PCle gen1 and gen2 protocols need 20% overhea, so the datalink rate is made 2 GT/s and 4 GT/s respectively. There two problems noticed in gen3. Increase the signaling rate to 10 GT/s with same overhead for the protocol or indicate the lower signaling rate of 8 GT/s with lower encoding overhead.
After the analysis, the technical feasibility of sealing PCle interconnect bandwidth, the group determined that 8 GT/s is manufactured by silicon process technology.
By enhancing the coding from 8b/10b to 128b/130b, the new protocol reduces the encoding overhead to 1 to 2 %. Hence, PCle gen3 provide datalink rate of 7.99 GT/s, thereby doubling the link rate from PCle gen2. So, for this purpose we did not immediately go to 128b130b encoding in earlier generations.
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