You will implement your ALU in behavioral VHDL using the Quartus II software. Th
ID: 3797071 • Letter: Y
Question
You will implement your ALU in behavioral VHDL using the Quartus II software. This file is what you will then use later in the semester when you need an ALU for your processor. You should create one VHDL (alu32.vhd) that has exactly the same format as follows.
a, b : in STD_LOGIC_VECTOR(31 downto 0);
ALUControl : in STD_LOGIC_VECTOR(1 downto 0);
Result : buffer STD_LOGIC_VECTOR(31 downto 0);
ALUFlags : out STD_LOGIC_VECTOR(3 downto 0)
);
end alu32;
You need to finish the following architecture of the above entity. Please finish the following lines with “???”. Read the comments and add the missing operations.
architecture behavioral of alu32 is
signal condinvb: STD_LOGIC_VECTOR(31 downto 0);
signal sum: STD_LOGIC_VECTOR(32 downto 0);
signal neg, zero, carry, overflow: STD_LOGIC; begin
begin
condinvb <= not b when (ALUControl(0) = '1') else b;
sum <= unsigned('0' & a) + unsigned('0' & condinvb) + ALUControl(0);
end process;
neg <= ????;
zero <= '1' when (Result = x"00000000") else '0'; carry <= ????;
overflow <= ????;
ALUFlags <= (neg, zero, carry, overflow);
end;
Fill in the ? with the necessary code.
Explanation / Answer
library ieee; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_arith.all; entity alu32 is port( a, b : in STD_LOGIC_VECTOR(31 downto 0); ALUControl : in STD_LOGIC_VECTOR(1 downto 0); Result : buffer STD_LOGIC_VECTOR(31 downto 0); ALUFlags : out STD_LOGIC_VECTOR(3 downto 0) ); end alu32;
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