4.11 Consider the following loop. loop :1 w r1,0(r1) and r1.rl.r2 1 1,0(r1) 1 1,
ID: 3792598 • Letter: 4
Question
4.11 Consider the following loop. loop :1 w r1,0(r1) and r1.rl.r2 1 1,0(r1) 1 1,0(r1) beq rl.ro loop Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, and that the pipeline has full forwarding support. Also assume that many iterations of this loop are executed before the loop exits. 4.11.1 [10] Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the first instruction of that iteration up to (but not including) the cycle in which we can fetch the first instruction of the next iteration. Show all instructions that are in the pipeline during these cycles (not just those from the third iteration). 4.11.2 [10]Explanation / Answer
a)
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
Loop
LW r1, 0(r1)
IF
ID
EX
MEM
WB
ANDr1,r1,r2
IF
*
ID
EX
MEM
WB
LW r1,0(r1)
IF
ID
EX
MEM
WB
LW r1,0(r1)
IF
*
ID
EX
MEM
WB
beq r1, r0,LOOP
IF
*
*
ID
EX
MEM
WB
The branch outcome is available at ID stage , and each iteration requires 7 cycles to complete.
b) In the pipeleine execution diagram the cycles are not having all five pipeline stages useful any useful work.
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
Loop
LW r1, 0(r1)
IF
ID
EX
MEM
WB
ANDr1,r1,r2
IF
*
ID
EX
MEM
WB
LW r1,0(r1)
IF
ID
EX
MEM
WB
LW r1,0(r1)
IF
*
ID
EX
MEM
WB
beq r1, r0,LOOP
IF
*
*
ID
EX
MEM
WB
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