The MIPS architecture doesn\'t support the addressing modes below. Synthesize th

Question

The MIPS architecture doesn't support the addressing modes below. Synthesize these instructions by writing a few MIPS lines that do the same functionality. Reduce the number of MIPS instructions used. Use registers (tx) instead of (Rx). For example, use t1 instead of R1. Load Rl, (R2)//Register indirect addressing mode Load R1, @(R2)//Memory indirect addressing mode Load R1, (R2)+//Auto increment addressing mode; data is 16-bit Load R1, (R2+R3+200)//Indexed with displacement addressing mode Load R1, (0xll22AABB)//Direct addressing mode

Explanation / Answer

1) Load R1,(R2) ----------------> Content of Memory[R2] is moved to R1

MIPS code

lw $t1,0($t2) # Load content of Memory[$t2+0] is loaded to $t1

2)Load R1,@(R2)-----------------> R1<-Memory[Memory[R2]]

MIPS code

lw $t3,0($t2) # Load content of Memory[$t2] is loaded to $t3

lw $t1,0($t3)   # Load content of Memory[$t3] is loaded to $t1

3)Load R1,(R2)+ -------------------> R1<-Content of Memory[R2] then R2<-R2+size

MIPS Code

li $t3,size #load $t3 with immediate value 'size'

lw $t1,0($t2) #load register $t1 with content of Memory[$t2]

add $t2,$t2,$t3 # $t2<-$t2+$t3

4)Load R1,(R2+R3+200) ----------->R1 is loaded with content of memory[R2+R3+200]

MIPS Code

li $t3,200 # load $t3 with immediate value 200

add $t3,$t3,$t2 #add content of $t3 and $t2 and place result in $t3

lw $t1,0($t3) #load $1 with content of address of memory[$t3]

5)Load R1,(0x1122AABB) -----------------> Load R1 with content of memory 0x1122AABB

MIPS Code

ori $t2,$t2,0xAABB # OR operation on 0x011220000 (which is in $t1 after executing

lui instruction) to 0x0000AABB

lw $t1,0($t2) #loads contents of memory[$t2] to $t1

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