I am running this on Xilinx 14.7 (Verilog) and was wondering why I get a syntax
ID: 3785830 • Letter: I
Question
I am running this on Xilinx 14.7 (Verilog) and was wondering why I get a syntax error saying the following.
ERROR:HDLCompiler:806 - Line 45: Syntax error near "reg".
ERROR:HDLCompiler:806 - Line 48: Syntax error near ",".
ERROR:HDLCompiler:806 - Line 49: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 50: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 51: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 52: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 53: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 54: Syntax error near ":".
ERROR:HDLCompiler:806 - Line 56: Syntax error near "default".
ERROR:HDLCompiler:806 - Line 57: Syntax error near "endcase".
This is my code...
module lab2B_VM(ALUOp, Opcode_Field, ALU_Operation);
//inputs
input [1:0] ALUOp;
input [10:0] Opcode_Field;//5:0
//outputs
output [3:0] reg ALU_Operation;//reg before ALU
always @ (ALUOp, Opcode_Field) begin
case (ALUOp,Opcode_Field) //case statements should also have Opcode field
13'b10_10001011000: ALU_Operation <= 2; //add--
13'b10_11001011000: ALU_Operation <= 6; //subtract--
13'b10_10001010000: ALU_Operation <= 0; //and--
13'b10_10101010000: ALU_Operation <= 1; //or--
13'b10_11101010000: ALU_Operation <= 12;//nor--
13'b10_11101010000: ALU_Operation <= 7; //stl // Pass B --
default: ALU_Operation <= 15; //should not happen
endcase
end
endmodule
Explanation / Answer
design verification process:
module
counter(CLOCK, DIRECTION, COUNT_OUT);
input
CLOCK;
input
DIRECTION;
output
[3:0] COUNT_OUT;
);
reg
[3:0] count_int = 0;
always
@(
posedge
CLOCK)
if
(DIRECTION)
count_int <= count_int + 1;
else
count_int <= count_int - 1;
assign
COUNT_OUT = count_int;
endmodule
.
Connect the 5V DC power cable to the power input on the demo board (J4).
2.Connect the download cable between the PC and demo board (J7).
3.Select Implementation from the drop-down list in the Sources window.
4.Select counter in the Sources window.
5.In the Process window, double-click the Configure Target Device process.
6.The Xilinx WebTalk Dialog box may open during this process. Click
Decline
7.In the Welcome dialog box, select
Configure devices using Boundary-Scan (JTAG).
8.Verify that Automatically connect to a cable and identify Boundary-Scan chain
is selected.
9.Click Finish.
10. If you get a message saying that there are two devices found, click OK
to continue.
The devices connected to the JTAG chain on the board will be detected and displayed
in the iMPACT window.
11. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click
Open.
12. If you get a Warning message, click OK.
13. Select Bypass to skip any remaining devices.
14. Right-click on the xc3s200
device image, and select Program...
The Programming Properties dialog box opens.
15. Click OK to program the device.
When programming is complete, the Program Succeeded message is displayed.
On the board, LEDs 0, 1, 2, and 3 are lit,indicating that the counter is running.
16. Close iMPACT without saving.
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