Using Logicworks, design and implement a state machine whose output is the 3-bit
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Question
Using Logicworks, design and implement a state machine whose output is the 3-bit gray code counter sequence. The output of the counter updates upon each positive edge of a clock signal. A 3-bit gray code counter has the following output sequence: 000 001 011 010 110 111 101 100 000 ... Once the sequence reaches 100, it loops back to 000. Use D-Flip Flops to hold the states of the state machine. Make sure that the state update equations are simplified as much as possible using K-maps, and use logic gates to implement the simplified state update equations. Use a binary switch for the clock input, and attach binary probes to the outputs.Explanation / Answer
STATE MACHINE DESIGN A 3-BIT GRAY CODE COUNTER
There are two basic components in a state machine, Memory which are usually D Flip-Flops, and Combinational Logic. To design a state machine, the D flipflops are usually a counter which is a device that is known. The following procedure will allow us to design the combinational logic necessary to allow the counter to sequence through the binary patterns that we desire.
THE STATE DIAGRAM
It shows the progression of states and the input and outputs. The arrow in the center shows the direction of the counter. However, it is possible to progress through the state table in the reverse order. If we start at 000, the next state is 001. From 001 the next state is 011. We progress through all possible states until the sequence repeats. We use the State Diagram to create the Next State Table
NEXT STATE TABLE
Fig1:
PRESENT STATE NEXT STATE
QC QB QA QC QB QA
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
TABLE 1
Table 1 contains the Next State Table for a 3-bit Gray Code Generator, and is created from the State
Diagram. It merely lists or specifies the output after the next clock pulse for a specific binary pattern
The Transition Table shows the flip-flop inputs required to make the counter go from the present state to the proper next state.
Each transition can be accomplished by possible conditions:
we can have a 0 to 1 transition by Setting the flip-flop or by Toggling the flip-flop.
If you can use the logic gates, you can do this way:
Extract from the truth table the logic function that defines each bit of the next state from the previous state: b0(n)=f(b0(n1),b1(n1),b2(n1))
Create the logic network that implement the 3 logic functions that you have found;
Now put it in a feedback from the output to the input of 3 D flip-flops, so then at each clock edge the state will be updated;
Reset the circuit to the 000 state.
If you know logic gates, flip flops and counters, you can easily understand how this circuit works.
Fig2:
when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.
The least significant bit (GCODE0) of the gray code is newly added and the frequency of the least significant bit (GCODE0) is a frequency one-half of a frequency of the reverse clock CKB with respect to the reference clock CK. As a result, it is possible to increase the bit length of the gray code by one bit without doubling a frequency of the reference clock CK .
K-map
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