The following are true/false questions. Please write either T or F on the line.

ID: 3777761 • Letter: T

Question

(a) Capacity misses can be eliminated by increasing cache associativity.

(b) Write-through caches are typically no-write-allocate, whereas write-back caches are typically write-allocate.

(d) When a data item is written repeatedly, a write-through cache probably will have better performance than a write-back cache.

(e) The clock speed for a pipelined architecture is determined by the speed of the fastest stage of the pipeline.

(f) A pipelined machine’s ISA should be logically identical to the non-pipelined version.

(g) Load/use is an example of a control hazard in a pipeline.

(h) Forwarding eliminates the needs for bubbles in the Y86 pipeline.

(i) Locality means that programs tend to reference data and instructions near those recently referenced.

(j) Flash memory is volatile, but DRAM is not

(a) Capacity misses can be eliminated by increasing cache associativity.

sol: TRUE

c)Potential memory aliasing may be an optimization blocker

sol:TRUE

(g) Load/use is an example of a control hazard in a pipeline

sol: FALSE

(j) Flash memory is volatile, but DRAM is not

sol: FALSE . DRAM is volatile memory

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