Question 5(22 points) Assume that individual stages of the data path have the fo

Question

Question 5(22 points) Assume that individual stages of the data path have the following latencies: IF:350ps ID: 450ps EX: 250ps MEM: 400ps WB: 200ps Also, assume that instructions executed by processor are broken down the as follows: alu 45% beq:20% lw:20% sw:15% is the clock cycle time in a pipelined and non-pipelined proces- sor? (4 points) b) What is the total latency of an Lw instruction in a pipelined and non- pipelined processor?(4 points) c) If we can split one stage of the pipelined data path into two new stages, each with half the latency of the original stage, which stage would you split

Explanation / Answer

a) What is the clock cycle time in a pipelined and non-pipelined process-sort?

Answer:-

Pipelined: cycle time determined by slowest stage: 400ps.

Non-pipelined: cycle time determined by sum of all stages: 1010ps.

(b) What is the total latency of the lw instruction in a pipelined and non-pipelined
processor?

Answer:-

LW instruction uses all 5 stages.
Pipelined processor takes 5 cycles at 400ps per cycle for total latency of 2000ps.
Non-pipelined processor takes 200+120+190+400+100 = 1010ps.

(c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

Answer:-

Split Memory Access stage into two stages of 200ps. New clock cycle time is 200ps.

Assume a fixed-size processor cache with two alternative configurations (direct-mapped and 2- way set associative), each with total size of 4 blocks, where each cache block is 16-bytes (4 32- bit MIPS words) wide.

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