A byte-addressable computer has a small data cache capable of holding eight 32-b

Question

A byte-addressable computer has a small data cache capable of holding eight 32-bit
words. Each cache block consists of one 32-bit word. When a given program is executed,
the processor reads data sequentially from the following hex addresses:
200, 204, 208, 20C, 2F4, 2F0, 200, 204, 218, 21C, 24C, 2F4
This pattern is repeated four times.
(a) Assume that the cache is initially empty. Show the contents of the cache at the end of
each pass through the loop if a direct-mapped cache is used, and compute the hit rate.
(b) Repeat part (a) for an associative-mapped cache that uses the LRU replacement algorithm.
(c) Repeat part (a) for a four-way set-associative cache.

Explanation / Answer

There are nine misses on the first pass and two misses on each of the subsequent passes. The hit rate is 69%.

b)

The hit rate was 44%.

C)

the first four cache entries are set 0 and the second four entries are set 1.

The hit rate was 63%.

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