1. Suppose that in 100 memory references there are 4 times misses in the first l

Question

1. Suppose that in 100 memory references there are 4 times misses in the first level cache and 2 misses in the second level cache. What are the various miss rates?

a. L1 cache miss rate = 4% and L2 miss rate = 2%

b. L1 cache miss rate = 4% and L2 miss rate = 50%

c. L1 cache miss rate = 4% and L2 miss rate = 60%

d. L1 cache miss rate = 0.4% and L2 miss rate = 60%

2. Consider information in question 14 above, assume the miss penalty from L2 cache to the main memory is 200 cycles, the hit time to L2 cache is 10 clock cycles, the hit time of L1 is 1 clock cycle, and there are 1.5 memory references per instruction. What is the average memory access time AMAT?

Given, AMAT = Hit time L1 + Miss rate L1 x (Hit time L2 + Miss rate L2 x Miss penalty L2)

6.2

1.56

2.6

5.4 Clock Cycles

6.2

1.56

2.6

5.4 Clock Cycles

Explanation / Answer

Note:

in multi level cache , for memory reference

first it will check L!,

if found ===> done

else check in L2

if found ====> done

   else get from main memory

1)

for 100 memory references

there 4 misses for L1 and 2 misses in L2 cache

hence for 100 memory access 4 misses in l1 cache => L1 cache miss rate = 4%

these 4 , will go for L2 cache , here there are 2 misses

hence out of 4 , there are 2 misses in L2 cache

Hence L2 cache miss rate = 50%

Ans:

L1 cache miss rate = 4% and L2 miss rate = 50%

2)

given

Hit time L1 = 1cycle

Miss rate L1 = 0.04

Hit time L2 = 10 cycles

Miss rate L2 = 0.5

Miss penalty L2 = 100 cycles

AMAT = Hit time L1 + Miss rate L1 x (Hit time L2 + Miss rate L2 x Miss penalty L2)

= 1 + 0.04*( 10 + 0.5*200)

= 1 + 0.04 * 110

= 5.4 cycles

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