A CPU is designed to execute one instruction in the following 5 stages: (1) fetc

Question

A CPU is designed to execute one instruction in the following 5 stages: (1) fetch the next instruction from memory and save it in Instruction Register (IR); (2) modify Program Counter (PC) to point to the next instruction; (3) Decode the instruction in IR; (4) Fetch operands; (5) ALU performs the calculation. Assuming each stage needs 2ns to complete its job, How long does it take for this computer to complete one instruction execution? What's the MIPS this computer can achieve with this pipeline (parallelism) design.

Explanation / Answer

a) As we have five stages and each stage take 2ms. So, to complete one instruction
execution it take 10ns.

b)
Normally MIPS for pipelining is contain five stages:
Instruction fetch (IF)
Instruction decode and register read (ID)
ALU Execution (ALU)
Data memory read or write (MEM)
Write result back into register (WB)

****** But we can further expanded to 8 stages ***********

instruction fetch ---.> First half
Instruction fetch ---> Second half
register fetch
Instruction execute
Data Cache access ---> First half
Data Cache access --> second half
tag checking
write back

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