You need to build a module in the code below that helps you input the 4 values a
ID: 3768403 • Letter: Y
Question
You need to build a module in the code below that helps you input the 4 values and output the 2 outputs. You also need to send a “done” signal when your code is complete and start on a “start signal”
Verilog code
module your _module(clk, rst, a, b, c, d, g, h, start, done);
input clk, rst;
input [15:0]a;
input [15:0]b;
input [15:0]c;
input [15:0]d;
output [15:0]g;
output [15:0]h;
reg [15:0]g;
reg [15:0]h;
input start;
output done;
reg done;
always @(posedge clk or negedge rst)
if (rst == 1'b0)
begin
g <= 16'd0;
h <= 16'd0;
done <= 1'b0;
end
else
begin
if (start == 1'b1)
begin
g <= a + b;
h <= c + d;
done <= 1'b1;
end
end
endmodule
C-Code you will need to translate into the Verilog module above
int main()
{
int I;
int j;
int a,b,c,d; //userinputs
int g,h; //led outputs
for(i = 3; i<105; i++)
{
j=b;
while(j<=102)
{
If(is_odd_parity(a))
{
g=mod(c,i);
}
else
{
h=max(c,i,c,b);
}
j=j+3;
}
}
}
Methods:
Is_odd_partiy > returns a 1 if there is an odd number of binary 1’s and 0 if there is an even number
Example is_odd_parity(2) returns 1
Mod(c,i) > is the modulo operator. It can divide one number by another and the result is the remainder. Example: 5%2 =1. You cannot use the % operator in Verilog to implement this functionality and will need to build it with gates(cant use 1pm modules either)
Max(c,i,c,b) > finds the maximum value of four values . Example: max(1,-2,3,4) returns 4
Explanation / Answer
module max (input [7:0] a, input [7:0] b,input [7:0] c, input [7:0] d,output reg [7:0] out); always @* begin if (a>b & a<c & a<d) out = a;if (b<c & b<d) out = b; if (c<d) out = c;else out = d; end endmodule
always @* begin out1=in1/in2; out2=in1%in2; end
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