Problem Four Design a synchronous state machine which detects the serial bit seq

Question

Problem Four Design a synchronous state machine which detects the serial bit sequence of 1 0 0 1 on inputsignal A and produces a “Moore-type” positive-logic output of Y equal to 1 (and lasting just one clockperiod) only when that particular bit sequence is observed. At all other times, the output Y should be 0.The final 1 of the sequence 1 0 0 1 can persist and become the first 1 of the next bit sequence, if A is still1 on the next tick of the clock. Note that the input signal A is asynchronous; that is, it can change valueat any time, independent of the clock

.a) Provide an ASM chart of your design, including the state assignments/encodings.

b) Implement your design in Verilog, using a synchronous Clear capability to ensure that your machine can be started at a known, valid initial state.

c) Provide a Verilog test bench and simulation waveform output to demonstrate the ability of yourmachine to correctly identify the input sequence, and to keep the output Y to 0 when anincorrect input sequence is provided.

Explanation / Answer

'defines0 3'b1001//wxyz=1001

module a_syn (clr,clk w x,y,z);

input clk,clr;

output w,x,y,z;

reg w,x,y,z;

reg[2:0]present_state;

always@(present _state)

begin

case (present_state)

s0:{w,x,y,z}=4'b1000;

endcase

end

                                                                                         testbench:

mouletest_a_syn()

reg clk,clr;

wire w,x,y,z;

initial

begin

clk=1'b0;

clr1'b0;

#3 clr1'b0;#5$stop;

end

always #2clk=~clk;

endmodule

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