Question is rom the book: Computer Organization and Architecture Designing for P

Question

Question is rom the book: Computer Organization and Architecture Designing for Performing, Ninth Edition

149 14.9 A pipelined A pipelined processor has a clock rate of 2.5 GHz and executes a program with 1.5 million instructions. The pipeline has five stages, and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out-of-sequence executions a. What is the speedup of this processor for this program compared to a nonpipe- lined processor, making the same assumptions used in Section 14.4? b. What is throughput (in MIPS) of the pipelined processor?

Explanation / Answer

(a).
clock rate = 2.5 GHz
no of instructions = 1.5 million

timing for passing through one stage :-
2.5 * 10^9 instructions ~~ 1 s
(2.5 * 10^9)/(1.5 * 10^6) ~~ 1.66 ms

timing in Non-pipelined = 5 * 1.66
timing in pipelined = 1.66

Speedup = timeNP/timeP = 5 times sppedup

(b).
Throughput = (Total instructions processed)/(Total time)
= (1.5 * 10^6 instructions)/(1.66 ms)
= ~ 1,000,000 instructions per ms

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