We will look at the different ways capacity affects overall performance. In gene
ID: 3765299 • Letter: W
Question
We will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70ns. And the percentage of memory instructions with respect to all instructions is 36%. The following table shows information for L1 caches attached to each of two processors, P1 and P2.
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KB
7.5%
0.55 ns
P2
4 KB
7.0%
1.70 ns
a. Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?
b. What is the Average Memory Access Time for P1 and P2 in terms of nano second?
c. Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KB
7.5%
0.55 ns
P2
4 KB
7.0%
1.70 ns
Explanation / Answer
A)
Clock rate for the L1 cache will be given by 1/(L1 hit rate)
For P1 it will be
1/0.55ns = 1.8181 Ghz
for P2 it will be
1/1.70 ns = 0.5882 Ghz
b)
Average Memory Access time = Hit Rate * Hit Time + Miss Rate * Miss time
for P1 we know that miss rate = 7.5%
so hit rate will be 100-7.5 = 92.5%
AMAT = 92.5 * 0.55 + 7.5*70 = 0.50875+5.25 = 5.75875 ns
for P2 we know that miss rate is 7%
so hit rate will be 100-7 - 93%
AMAT = 93 * 1.7 + 7 * 70 = 1.581 + 4.90 = 6.481 ns
C)
We know that
Miss cycles = (IC)*(Memory Access Freq)*(Miss Rate)*(Main Memory Access/L1 Hit Time)
For P1 it will be
Miss cycles = (IC)*(Memory Access Freq)*(Miss Rate)*(Main Memory Access/L1 Hit Time)
=0.36 * (0.075) * (70/0.55)
=IC * 3.4363
Total cycles = 1 * IC + 3.4363 * IC = 4.4363 IC
CPI = Total Cycles / Instruction Count = 4.4363
CPU Time with stalls = IC * CPI * Clock Cycle
= IC * CPI * L1 Hit Time
= IC * 4.4363 * .55 = 2.44IC
for P2 it will be
Miss cycles = (IC)*(Memory Access Freq)*(Miss Rate)*(Main Memory Access/L1 Hit Time)
=0.36 * (0.07) * (70/1.70)
=IC * 1.03764
Total cycles = 1 * IC + 1.03764 * IC = 2.03764 IC
CPI = Total Cycles / Instruction Count = 2.03764
CPU Time with stalls = IC * CPI * Clock Cycle
= IC * CPI * L1 Hit Time
= IC * 2.03764 * 1.70 = 3.464 IC
Since for P1 CPU Time is less therefore P1 is faster.
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