A microprogrammed processor has the following parameters. Generating the startin
ID: 3765093 • Letter: A
Question
A microprogrammed processor has the following parameters. Generating the starting
address of the microroutine of an instruction takes 2.1 ns, and reading a microinstruction
from the control store takes 1.5 ns. Performing an operation in theALUrequires a maximum
of 2.2 ns, and access to the cache memory requires 1.7 ns. Assume that all instructions and
data are in the cache.
(a) Determine the minimum time needed for each of the steps in Figure 5.26.
(b) Ignoring all other delays, what is the minimum clock cycle that can be used for this
processor?
Figure5.26: https://www.dropbox.com/s/6s85opd8t5i8b29/5.26.png?dl=0
Explanation / Answer
All of these components with the exception of the user terminal are packaged in a small cabinet which is an unobtrusive addition to a normal office. The terminal, keyboard, and pointing device are packaged for desktop use (Figure 1).
The Alto has led to an entirely new computing environment. Many applications devote the entire machine to interacting with a user and satisfying his needs; examples are document production and illustration, interactive programming, animation, simulation, and playing music. These individual applications are supplemented by a large number of services available via communications; examples are printing service, mailbox services for delivering electronic mail, and bulk file storage services. The Ethernet has also given rise to applications that use several Altos concurrently to furnish additional computing power or to allow several people at their machines to interact with one another.
The principal characteristics of the Alto processor are described in Section 2. Sections 3 to 6 describe input-output controllers for the display, disk, Ethernet, and printer. Section 7 surveys the environment and applications that grew up for the Alto. Section 8 offers a brief retrospective look at the design.
Figure 1. The Alto personal computer, showing a user at work with the display, mouse, and keyset.
2. The Alto processor
The major applications envisioned for the Alto were interactive text editing for document and program preparation, support for the program development process, experimenting with real-time animation and music generation, and operation of a number of experimental office information systems. The hardware design was strongly affected by this view of the applications. The design is biased toward interaction with the user, and away from significant numerical processing: there are extensive user input-output facilities, but no hardware for arithmetic other than 16-bit integer addition and subtraction.
The processor is microcoded, which permitted the machine to start out with rather powerful facilities, and also allows easy expansion as new capabilities are required. The amount of control store provided has evolved over time as shown in Figure 2. Initially, the machine contained only 1K words, implemented with PROM. The most recent version provides 4K words, of which 1K is implemented with PROM, and 3K is RAM.
1973
The micromachine is shared by sixteen fixed priority tasks. The emulator, which interprets instructions of the user's program, is the lowest priority task; the remaining tasks are used for the microcoded portions of input-output controllers and for housekeeping functions. Control of the micromachine typically switches from one task to another every few microseconds, in response to wakeup requests generated by the rio controllers. The emulator task requests a wakeup at all times, and runs if no higher priority task requires the processor. There is usually no overhead associated with a task switch, since the microprogram counters (MPCs) for all tasks are stored in a special high speed RAM, the MPC RAM. The main memory is synchronous with the processor, which controls all memory requests.
The task switching mechanism provides a way of multiplexing all the system resources, both processor and memory cycles, among the consumers of these resources. In most small systems with single-ported memories, the memory is multiplexed among the I/0 controllers and the CPU, and when an 1/0 controller is accessing the memory, the CPC is idle. In the Alto, the processor is multiplexed, and multiplexing of the memory is a natwal consequence. By sharing the hardware in this way, it has been possible to provide more capable logical interfaces to the Ito devices than are usually found in small machines, since the 1/0 controllers have the full processing capability and temporary •storage of the micromachine at their disposal.
The standard Alto contains controllers for the disk, the display, and the Ethernet. The disk controller uses two tasks. the display and the cursor use a total of four tasks, and the Ethernet uses one task. In addition to the emulator task, there is a timed task that is awakened every 38 /Is, and a fault task that is awakened whenever a memory error occurs and is responsible for logging the error and generating an interrupt. The timed task refreshes the main memory, and maintains the real-time clock and an interval timer accessible from the emulator.
The main memory size of the Alto was initially 64K 16-bit words, implemented with 1K bit semiconductor RAM chips. As semiconductor technology improved, the memory size was increased, as shown in Figure 2. The initial version of the machine provided parity checking; later configurations employ single error correction and double error detection. Memory access time is 850ns (five microinstruction cycles), and either one or two words can be transferred during a single memory cycle. In machines with more than 64K, access to extended memory is provided via bank registers accessible to the micromachine; the standard instruction set and I/0 controller microcode make use of the additional' memory only in limited ways. The reason for this clumsy arrangement is that the lifetime of the Alto has been longer than originally anticipated, and the additional memory was an unplanned addition.
Because the machine was intended for personal use, protection and virtual memory facilities normally included to support sharing were omitted from the Alto.
The multitasking structure of the processor led to an extremely simple implementation. The processor is contained on five printed circuit boards, each of which contains approximately 70 small and medium-scale TIT integrated circuits. Each of the three standard I/0 controllers occupy a board with about 60 ICS. The main memory uses 312 chips.
1973
The micromachine is shared by sixteen fixed priority tasks. The emulator, which interprets instructions of the user's program, is the lowest priority task; the remaining tasks are used for the microcoded portions of input-output controllers and for housekeeping functions. Control of the micromachine typically switches from one task to another every few microseconds, in response to wakeup requests generated by the rio controllers. The emulator task requests a wakeup at all times, and runs if no higher priority task requires the processor. There is usually no overhead associated with a task switch, since the microprogram counters (MPCs) for all tasks are stored in a special high speed RAM, the MPC RAM. The main memory is synchronous with the processor, which controls all memory requests.
The task switching mechanism provides a way of multiplexing all the system resources, both processor and memory cycles, among the consumers of these resources. In most small systems with single-ported memories, the memory is multiplexed among the I/0 controllers and the CPU, and when an 1/0 controller is accessing the memory, the CPC is idle. In the Alto, the processor is multiplexed, and multiplexing of the memory is a natwal consequence. By sharing the hardware in this way, it has been possible to provide more capable logical interfaces to the Ito devices than are usually found in small machines, since the 1/0 controllers have the full processing capability and temporary •storage of the micromachine at their disposal.
The standard Alto contains controllers for the disk, the display, and the Ethernet. The disk controller uses two tasks. the display and the cursor use a total of four tasks, and the Ethernet uses one task. In addition to the emulator task, there is a timed task that is awakened every 38 /Is, and a fault task that is awakened whenever a memory error occurs and is responsible for logging the error and generating an interrupt. The timed task refreshes the main memory, and maintains the real-time clock and an interval timer accessible from the emulator.
The main memory size of the Alto was initially 64K 16-bit words, implemented with 1K bit semiconductor RAM chips. As semiconductor technology improved, the memory size was increased, as shown in Figure 2. The initial version of the machine provided parity checking; later configurations employ single error correction and double error detection. Memory access time is 850ns (five microinstruction cycles), and either one or two words can be transferred during a single memory cycle. In machines with more than 64K, access to extended memory is provided via bank registers accessible to the micromachine; the standard instruction set and I/0 controller microcode make use of the additional' memory only in limited ways. The reason for this clumsy arrangement is that the lifetime of the Alto has been longer than originally anticipated, and the additional memory was an unplanned addition.
Because the machine was intended for personal use, protection and virtual memory facilities normally included to support sharing were omitted from the Alto.
The multitasking structure of the processor led to an extremely simple implementation. The processor is contained on five printed circuit boards, each of which contains approximately 70 small and medium-scale TIT integrated circuits. Each of the three standard I/0 controllers occupy a board with about 60 ICS. The main memory uses 312 chips.
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