Problem Design Using VHDL Programming You are to design a Moore network to contr

Question

Problem Design Using VHDL Programming

You are to design a Moore network to control a vending machine. The machine only dispenses product that costs 25 cents. The Moore network has 3 inputs: N, D, and Q (nickel, dime and quarter inputs) and three outputs, P, V, X (dispense product, and dispense change in dimes or nickels). V and X (Roman numerals) represent one nickel or one dime dispensed. The coin detector mechanism in the vending machine is synchronized with the clock in the network you are to design. The coin detector outputs a single 1 for N, D, or Q for each nickel, dime, or quarter, respectively, that the customer inserts. Only one input will be 1 at any time. When the customer has inserted at least 25¢ in any combination of nickels, dimes and quarters, the machine dispenses one yummy piece of candy and gives any change due. The change may be dispensed in nickels or dimes. For each 1 output on V, the customer is issued one nickel, and for each 1 output on X, the customer is issued a dime. For each 1 output on P, the delicious candy is dispensed. After dispensing the product, the network resets.

Notes:

any number of 0's can occur between the 1's on the inputs

you may assume that the customer will not insert any more coins once the machine is dispensing change

nickels and dimes should not be dispensed as change during the same clock cycle; product may be dispensed at the same time as a nickel or dime

Explanation / Answer

VHDL stands for VHSIC hardware description language.VHSIC means very-high-speed integrated circuit.As the name suggests it is a hardware description language used to model a digital system.VHDL is commonly used to write text models that describe a logic circuit. VHDL is aDataflow language, (i.e. models a program as a directed graph of the data flowing between operations). unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.VHDL is a language that can be understood by hardware

Design Flow

It is not necessary to base all of your design for a programmable device on VHDl. Some tools allow you to mix VHDl with schematics. Others allow you to mix VHDL with other HDL such as Verilog. You may also design part of your circuit using ABEL for example. One senerio allows you to compile all description in VHDL, ABEL, schematics into a gate level netlist which can be tehn used for gate-level simulation. Usually vendors will offer solution such as we have mentioned on a PC based system and the tools is usually very inexpensive. This is a low risk way of entering into VHDL design. But usually this approach does not support large designs well.

The second method of introducing VHDL is to describe a complete device with the language and to simulate the VHDL code as well as synthesizing the design. This is the approach we have taken in this class even though our designs are relatively small anyway. With this method, one should simuate the original design and the synthesized design using the same stimulus. A standard called VITAL exists for describing gate level cells in VHDL. Most of the programmable vendors have VITAL based libraries available. You should make sure your tools (simulation) can accept VITAL libraryies. Nowadays tools are supported by both PC platforms and wrkstations. Using tools on PC does not have any disadvantge anymore in some cases it have many advantages.

Synthesis Tool Gotcha!

Consider the following VHDL code:

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