The following is the verilog code for a 15 bit 2 to 1 multiplexer. When the sele
ID: 3758185 • Letter: T
Question
The following is the verilog code for a 15 bit 2 to 1 multiplexer. When the selector is 0 the output f is i0 and when the selector is 1 the output is i1.
module mux2to1(i0, i1, s, f);
input i0, i1, s;
outputf;
assignf= s ? i1 : i0;
endmodule
Modify this code to build a 15 bit 4 to 1 multiplexer. The multiplexer will! have the following specification:
Four 15 bit data inputs, W0, W1, W2 and W3.
One 25 bit selector input, S[1..0].
One 15 bit output, F.
When S [1..0] = 00 the output will be W0.
When S [1..0] = 01 the output will be W1.
When S [1..0] = 10 the output will be W2.
When S [1..0] = 11 the output will beW3.
Explanation / Answer
module full
(sel, i1, i2, i3, i4, o1);
input [1:0] sel;
input [1:0] i1, i2, i3, i4;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3 or i4)
begin
case (sel)
2'b00: o1 = i1;
2'b01: o1 = i2;
2'b10: o1 = i3;
2'b11: o1 = i4;
endcase
module notfull
(sel, i1, i2, i3, o1);
input [1:0] sel;
input [1:0] i1, i2, i3;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3)
begin
case (sel)
2'b00: o1 = i1;
2'b01: o1 = i2;
2'b10: o1 = i3;
endcase
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