Verilog Project 1 Part 1: 8-bit Adder in structural verilog Make an 8-bit ripple
ID: 3756280 • Letter: V
Question
Verilog Project 1
Part 1: 8-bit Adder in structural verilog
Make an 8-bit ripple carry adder in structural Verilog(hint: make one module for a full adder, and then make another top module and instantiate 8 full adders)
Part 2: 8x1 Multiplexer in behavioral Verilog
Make an 8x1 multiplexer in behavioral verilog(hint: use a case statement for the most straightforward implementation
all circuits must also have must be tested by an accompanying test bench which will test the circuit for all input combinations
Explanation / Answer
module ripple(a, b, cin, sum, cout);
input [07:0] a;
input [07:0] b;
input cin;
output [7:0]sum;
output cout;
wire[6:0] c;
add a1(a[0],b[0],cin,sum[0],c[0]);
add a2(a[1],b[1],c[0],sum[1],c[1]);
add a3(a[2],b[2],c[1],sum[2],c[2]);
add a4(a[3],b[3],c[2],sum[3],c[3]);
add a5(a[4],b[4],c[3],sum[4],c[4]);
add a6(a[5],b[5],c[4],sum[5],c[5]);
add a7(a[6],b[6],c[5],sum[6],c[6]);
add a8(a[7],b[7],c[6],sum[7],cout);
endmodule
module add(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule
TEST BENCH :
module rippleadder_b;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
ripple uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout) );
initial begin
#10 a=8b00000001;b=8b00000001;cin=1b0;
#10 a=8b00000001;b=8b00000001;cin=1b1;
#10 a=8b00000010;b=8b00000011;cin=1b0;
#10 a=8b10000001;b=8b10000001;cin=1b0;
#10 a=8b00011001;b=8b00110001;cin=1b0;
#10 a=8b00000011;b=8b00000011;cin=1b1;
#10 a=8b11111111;b=8b00000001;cin=1b0;
#10 a=8b11111111;b=8b00000000;cin=1b1;
#10 a=8b11111111;b=8b11111111;cin=1b0;
#10 $stop;
end
endmodule
module mux( Out,Sel, In1,In2,In3,In4, In5, In6, In7, In8);
input [7:0] In1,
In2,
In3,
In4,
In5,
In6,
In7,
In8;
input [2:0] Sel; //The three bit selection line
output [7:0] Out; //The single 8-bit output line of the Mux
reg [7:0] Out;
//Check the state of the input lines
always @ (In1 or In2 or In3 or In4 or In5 or In6 or In7 or In8 or Sel)
begin
case (Sel)
3'b000 : Out = In1;
3'b001 : Out = In2;
3'b010 : Out = In3;
3'b011 : Out = In4;
3'b100 : Out = In5;
3'b101 : Out = In6;
3'b110 : Out = In7;
3'b111 : Out = In8;
default : Out = 8'bx;
//If input is undefined then output is undefined
endcase
end
endmodule
`timescale 1ns / 1ps
module mux_tb;
// Inputs
reg [2:0] Sel;
reg [7:0] In1;
reg [7:0] In2;
reg [7:0] In3;
reg [7:0] In4;
reg [7:0] In5;
reg [7:0] In6;
reg [7:0] In7;
reg [7:0] In8;
// Outputs
wire [7:0] Out;
//temporary variable
reg [2:0] count = 3'd0;
// Instantiate the Unit Under Test (UUT)
mux uut (
.Out(Out),
.Sel(Sel),
.In1(In1),
.In2(In2),
.In3(In3),
.In4(In4),
.In5(In5),
.In6(In6),
.In7(In7),
.In8(In8)
);
initial begin
// Initialize Inputs
Sel = 0;
In1 = 0;
In2 = 0;
In3 = 0;
In4 = 0;
In5 = 0;
In6 = 0;
In7 = 0;
In8 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Sel = 3'd0;
In1 = 8'd0;
In2 = 8'd1;
In3 = 8'd2;
In4 = 8'd3;
In5 = 8'd4;
In6 = 8'd5;
In7 = 8'd6;
In8 = 8'd7;
//Selection input generation
for (count = 0; count < 8; count = count + 1'b1)
begin
Sel = count;
#20;
end
end
endmodule
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