Suppose the target assembly language for a compiler has these five Exercise inst

Question

Suppose the target assembly language for a compiler has these five Exercise instructions for integers: 4 load address, reg add reg, reg, reg sub reg, reg, reg mul reg, reg, reg store reg, address In these instructions, an address is the name of a static variable (whose actual address will be filled in by the loader). A reg is the name of an integer register, a special extra-fast memory location inside the processor. The target assembly language has three integer registers: r1, r2, and r3. The load instruction loads the integer from the given memory address into the given register. The add instruc- tion adds the second register to the first register and places the result in the third register. The sub instruction subtracts the second register from the first register and places the result in the third register. The mul instruction multiplies the first register by the second register and places the result in the third register. The store instruction stores the integer from the given register at the given memory ad- dress. So, for example, the compiler might translate the assignment result . offset + (width*n) into this: load width, rl load n, r2 mul rl,r2,rl load offset,r2 add r2,rl,rl store rl,result

Explanation / Answer

1.

load       gross,r1 ; Initialize the gross

load         costs,r2 ; initialize the costs

sub          r1,r2,r1 ; subtract the numbers and store it in r1

store        r1, net

2.

load       length,r1 ; Initialize the length

load         width,r2 ; initialize the width

mul           r1,r2, r1 ;multiply r1 and r2 and store the result in r1

load     height, r2 ; load height in r2

mul      r1, r2, r1; store the result of r1*r2 into r1

store r1, volume; store the final result in volume

3.

Load x,r1 ; initialize the length of cube

Load x,r2 ;

Mul r1,r2,r1; multiplies the number and stores the result in r1

Mul r1,r2,r1 ; multiplies the number again and stores the result in r1

Store r1, cube

4.

Load r1, a

Load r2, abase

Sub r1, r2,r1

Load r2, b

Load r3, bbase

Sub r2, r3, r2

Mul r1, r2, r1

Load r2,c

Load r3,cbase

Sub r2,r3,r2

Mul r1,r2,r1

Store r1, final

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