Q- Use the following information related to the five stages of our MIPS datapath
ID: 3746597 • Letter: Q
Question
Q- Use the following information related to the five stages of our MIPS datapath:
Instruction Fetch takes 400ps.
Instruction Decode takes 200ps.
Execute stage takes 200ps
Memory Stage (i.e., read and write data memory) takes 200ps
Write Back (i.e., writing a result in a register) takes 100ps.
a. For a single cycle design, what is the minimum clock cycle time for proper execution?
b. How much time does it take to implement the following code segment on the single cycle
design?
lw $1, 100($0)
lw $2 ,200($0)
lw $3, 300($0)
lw $4, 400($0)
c. For a 5-stage pipeline, what is the minimum clock cycle time for proper execution?
d. How much time does it take to implement the above code segment on the pipelined design?
Explanation / Answer
Answer is as follows :
a) For a single cycle design, what is the minimum clock cycle time for proper execution
As we know that there is only single cycle processing , so for one instruction, it takes :
400 + 200 + 200 + 200 + 100 = 1100 ps
b) How much time does it take to implement the following code segment on the single cycle
In this we have four instruction in single cycles.
So multily 1100 with 4.
We get 4400 ps
c. For a 5-stage pipeline, what is the minimum clock cycle time for proper execution?
Pipelining to 5 stages reduces the cycle time to the length of the longest stage.
So Clock cycle time for Proper Execution is 400 ps.
d. How much time does it take to implement the above code segment on the pipelined design?
The same procedure as part d is follows, but additional 100 ps of last WB stage is added to this.
So (400 * 4 ) + 100 = 1600 + 100 = 1700 ps.
if there is any query please ask in comments....
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