Wind tunnel measurements of the pressure and skin friction around a NACA 2415 ai

Question

Wind tunnel measurements of the pressure and skin friction around a NACA 2415 airfoil at 8 degrees angle of attack resulted in the following data of pressure and skin friction coefficients C) and C(1) at locations X) & YD over the airfoil. cf 1003 0.9974 0.9893 0.9759 0.95733 0.93377 0.00157 0.00223 0.00419 0.00739 0.01172 0.01705 0.02323 0.03006 0.00432 0.0126 0.0165 0.0211 0.0313 0.0279 0.1911 0.2321 0.83591 0.79536 0.75154 0.7049 0.65595 0.03738 0.04498 0.05267 0.261 0.06025 0.067530.3452 0.5043 -0.5467 0.7654 0.9391 0.9453 1.0876 -0.4233 0.07431 0.0804 0.08562 0.08978 0.09272 0.55331 0.44811 0.39597 0.24722 0.20261 0.16142 0.12411 0.09112 0.06282 0.03952 0.02145 0.00878 0.00161 0.09366 0.0914 0.08736 0.08163 0.07438 0.0658 0.05615 0.04566 0.0346 0.02319 0.01161 1.3233 1.4203 1.7688 1.8716 2.0511 2.2698 2.3861 2.6653 -0.544 0.3443 MacBook Pro

Explanation / Answer

1.

CPU Register:-

A processor register (CPU register) is one of a small set of data holding places that are part of the computer processor.

A register may hold an instruction, a storage address, or any kind of data (such as a bit sequence or individual characters). Some instructions specify registers as part of the instruction. For example, an instruction may specify that the contents of two defined registers be added together and then placed in a specified register.

A register must be large enough to hold an instruction - for example, in a 64-bit computer, a register must be 64 bits in length. In some computer designs, there are smaller registers - for example, half-registers - for shorter instructions. Depending on the processor design and language rules, registers may be numbered or have arbitrary names.

A processor typically contains multiple index registers, also known as address registers or registers of modification. The effective address of any entity in a computer includes the base, index, and relative addresses, all of which are stored in the index register. A shift register is another type. Bits enter the shift register at one end and emerge from the other end. Flip flops, also known as bistable gates, store and process the data.

Registers are the most important components of CPU. Each register performs a specific function. A brief description of most important CPU's registers and their functions are given below:

1. Memory Address Register (MAR):

This register holds the address of memory where CPU wants to read or write data. When CPU wants to store some data in the memory or reads the data from the memory, it places the address of the required memory location in the MAR.

2. Memory Buffer Register (MBR):

This register holds the contents of data or instruction read from, or written in memory. The contents of instruction placed in this register are transferred to the Instruction Register, while the contents of data are transferred to the accumulator or I/O register.

In other words you can say that this register is used to store data/instruction coming from the memory or going to the memory.

3. I/O Address Register (I/O AR):
I/O Address register is used to specify the address of a particular I/O device.

4. I/O Buffer Register (I/O I3R):

I/O Buffer Register is used for exchanging data between the I/O module and the processor.

5. Program Counter (PC)

Program Counter register is also known as Instruction Pointer Register. This register is used to store the address of the next instruction to be fetched for execution. When the instruction is fetched, the value of IP is incremented. Thus this register always points or holds the address of next instruction to be fetched.

6. Instruction Register (IR):

Once an instruction is fetched from main memory, it is stored in the Instruction Register. The control unit takes instruction from this register, decodes and executes it by sending signals to the appropriate component of computer to carry out the task.

7. Accumulator Register:

The accumulator register is located inside the ALU, It is used during arithmetic & logical operations of ALU. The control unit stores data values fetched from main memory in the accumulator for arithmetic or logical operation. This register holds the initial data to be operated upon, the intermediate results, and the final result of operation. The final result is transferred to main memory through MBR.

8. Stack Control Register:

A stack represents a set of memory blocks; the data is stored in and retrieved from these blocks in an order, i.e. First In and Last Out (FILO). The Stack Control Register is used to manage the stacks in memory. The size of this register is 2 or 4 bytes.

9. Flag Register:

The Flag register is used to indicate occurrence of a certain condition during an operation of the CPU. It is a special purpose register with size one byte or two bytes. Each bit of the flag register constitutes a flag (or alarm), such that the bit value indicates if a specified condition was encountered while executing an instruction.

For example, if zero value is put into an arithmetic register (accumulator) as a result of an arithmetic operation or a comparison, then the zero flag will be raised by the CPU. Thus, the subsequent instruction can check this flag and when a zero flag is "ON" it can take, an appropriate route in the algorithm.

Main Memory in MIPS:-

Mips has nothing to do with the storage. It is just the structure/architecture of the processor. When we say load word, we are getting data from main memory(RAM). This data will be stored temporarily in the registers during processing. Every processor has some registers which can store some data during processing. To summarize data is brought from main memory to processor(MIPS) registers, processed and then written back to main memory.

Now, when there is a cache in between processor and main memory, the processor checks the cache first for the data. If the data is not present in cache, it gets the data from main memory.

Modern computer systems nearly always use cache memory andvirtual memory. But our abstract view of memory does not include them. The purpose of virtual memory is to make it appear as if a program has the full address space available. So our programming model has the full address space. The purpose of cache is to transparently speed up memory access. So our programming model does not include cache. Memory in the programming model is as follows:

DATA:

MIPS memory is an array of 232 bytes. Each byte has a 32-bit address. Each byte can hold an 8-bit pattern, one of the 256 possible 8-bit patterns. The addresses of MIPS main memory range from 0x00000000 to 0xFFFFFFFF.

However, user programs and data are restricted to the first 231bytes. The last half of the address space is used for the operating system and for specialized purposes.

OPERATIONS:

The processor chip contains registers, which are electronic components that can store bit patterns. The processor interacts with memory by moving bit patterns between memory and its registers.

Load: a bit pattern starting at a designated address in memory is copied into a register inside the processor.
Store: a bit pattern is copied from a processor register to memory at a designated address.
Bit patterns are copied between the memory and the processor in groups of one, two, four, or eight contiguous bytes. When several bytes of memory are used in an operation, only the address of the first byte of the group is specified.

2.

Stack Pointer:-

A stack pointer is a small register that stores the address of the last program request in a stack. A stack is a specialized buffer which stores data from the top down. As new requests come in, they "push down" the older ones. The most recently entered request always resides at the top of the stack, and the program always takes requests from the top.

A stack (also called a pushdown stack) operates in a last-in/first-out sense. When a new data item is entered or "pushed" onto the top of a stack, the stack pointer increments to the next physical memory address, and the new item is copied to that address. When a data item is "pulled" or "popped" from the top of a stack, the item is copied from the address of the stack pointer, and the stack pointer decrements to the next available item at the top of the stack.

The actual implementation of a stack depends on the microprocessor architecture. It can grow up or down in memory and can move either before or after the push/pop operations.

Operation which typically affect the stack are:

subroutine calls and returns.
interrupt calls and returns.
code explicitly pushing and popping entries.
direct manipulation of the SP register.
Consider the following program in my (fictional) assembly language:

Addr Opcodes Instructions ; Comments
---- -------- -------------- ----------
; 1: pc<-0000, sp<-8000
0000 01 00 07 load r0,7 ; 2: pc<-0003, r0<-7
0003 02 00 push r0 ; 3: pc<-0005, sp<-7ffe, (sp:7ffe)<-0007
0005 03 00 00 call 000b ; 4: pc<-000b, sp<-7ffc, (sp:7ffc)<-0008
0008 04 00 pop r0 ; 7: pc<-000a, r0<-(sp:7ffe[0007]), sp<-8000
000a 05 halt ; 8: pc<-000a
000b 06 01 02 load r1,[sp+2] ; 5: pc<-000e, r1<-(sp+2:7ffe[0007])
000e 07 ret ; 6: pc<-(sp:7ffc[0008]), sp<-7ffe
Now let's follow the execution, describing the steps shown in the comments above:

This is the starting condition where the program counter is zero and the stack pointer is 8000 (all these numbers are hexadecimal).
This simply loads register r0 with the immediate value 7 and moves to the next step (I'll assume that you understand the default behavior will be to move to the next step unless otherwise specified).
This pushes r0 onto the stack by reducing the stack pointer by two then storing the value of the register to that location.
This calls a subroutine. What would have been the program counter is pushed on to the stack in a similar fashion to r0 in the previous step and then the program counter is set to its new value. This is no different to a user-level push other than the fact it's done more as a system-level thing.
This loads r1 from a memory location calculated from the stack pointer - it shows a way to pass parameters to functions.
The return statement extracts the value from where the stack pointer points and loads it into the program counter, adjusting the stack pointer up at the same time. This is like a system-level pop (see next step).
Popping r0 off the stack involves extracting the value from where the stack pointer points then adjusting that stack pointer up.
Halt instruction simply leaves program counter where it is, an infinite loop of sorts.
3.

Basic Block:-

In compiler construction, a basic block is a straight-line code sequence with no branches in except to the entry and no branches out except at the exit.This restricted form makes a basic block highly amenable to analysis. Compilers usually decompose programs into their basic blocks as a first step in the analysis process. Basic blocks form the vertices or nodes in a control flow graph.

Source codes generally have a number of instructions, which are always executed in sequence and are considered as the basic blocks of the code. These basic blocks do not have any jump statements among them, i.e., when the first instruction is executed, all the instructions in the same basic block will be executed in their sequence of appearance without losing the flow control of the program.

A program can have various constructs as basic blocks, like IF-THEN-ELSE, SWITCH-CASE conditional statements and loops such as DO-WHILE, FOR, and REPEAT-UNTIL, etc.

Basic block identification

We may use the following algorithm to find the basic blocks in a program:

1.Search header statements of all the basic blocks from where a basic block starts:

a.First statement of a program.

b.Statements that are target of any branch (conditional/unconditional).

c.Statements that follow any branch statement.

2.Header statements and the statements following them form a basic block.

3.A basic block does not include any header statement of any other basic block.

Basic blocks are important concepts from both code generation and optimization point of view.

Basic Blocks

Basic blocks play an important role in identifying variables, which are being used more than once in a single basic block. If any variable is being used more than once, the register memory allocated to that variable need not be emptied unless the block finishes execution.

Control Flow Graph

Basic blocks in a program can be represented by means of control flow graphs. A control flow graph depicts how the program control is being passed among the blocks. It is a useful tool that helps in optimization by help locating any unwanted loops in the program.

Control Flow Graph

4.
• Decision making instructions - alter the control flow • MIPS conditional branch instructions: bne and beq
Example: if (i == j)
h= i + j;

bne $s0, $s1, Label
add $s3, $s0, $s1
Label:

Control Instruction • MIPS unconditional branch instructions: j label
Example: if (i != j)
h = i + j;
else
h = i - j;

beq $s4, $s5, Lab1
add $s3, $s4, $s5 else
j Lab2  
Lab1: sub $s3, $s4, $s5
Lab2: ...
Comparison – less or greater:-
slt: set-if-less-than slt $t0, $s1, $s2
if $s1 < $s2 then $t0 = 1
else $t0 = 0
Can use this instruction to build
“ blt $s1, $s2, Label”,
“ble $s1, $s2, Label”

5.
Limitations Of Conditional Branch Instructions:-
For the branch instructions there are 16 bits available to specify the target address. These are stored as signed offsets relative to the instruction following the branch instruction (again with two bits of shifting applied, because it's unnecessary to store something that we know will always be 0). So the actual offset after restoring the 2 least significant bits is 18 bits, which then is sign-extended to 32 bits and added to the address of the instruction following the branch instruction. This makes is possible to branch to +/-128kB within the branch instruction.

So, if it would not be more efficient in general, it still could be more efficient in this particular exercise. I've thought about that, and I assumed that a jump instruction costs time, and therefore we'd want to minimize the amount of jumps needed. This means that, when we expect the condition to hold, we should use bne, and when we expect the condition to fail, we should use beq.

Now if we test whether $s3 equals $s4, when we have no information whatsoever about the content of those registers, it's not reasonable to assume that they're likely to be equal; on the contrary, it's more likely that they're not equal, which should result in using beq instead of bne.

So, to sum up: textbook says bne is more efficient than beq,

Both ADDI and BNE/BEQ are I-Type instructions. But whereas the immediate field in the ADDI instruction is used for storing the immediate operand for the addition, it's used for storing the branch offset in the case of BEQ/BNE.

There may be MIPS assemblers which allow you to use immediate operands in conditional branch instructions, but they will expand those pseudo-instructions into multiple actual instructions.

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