Hello! I have a problem with my verilog for ALU design, the compile is good, but
ID: 3746117 • Letter: H
Question
Hello! I have a problem with my verilog for ALU design, the compile is good, but when I enter simulate behavioral model, the ALUResult cant show...
module lab3cc(
input [1:0] ALUOp,
input [10:0] OpcodeField,
input [63:0] A,
input [63:0] B,
output reg [63:0] ALUResult,
output Zero
);
wire [3:0] ALUOperation;
ALUControl first(ALUOp, OpcodeField, ALUOperation);
ALU second(ALUOperation, A, B, ALUResult, Zero);
endmodule
module ALUControl(ALUOp, OpcodeField, ALUOperation);
input [1:0] ALUOp;
input [10:0] OpcodeField;
output reg [3:0] ALUOperation;
always @(ALUOp,OpcodeField )
begin
case(OpcodeField)
11'b10001011000: if(ALUOp>=2) assign ALUOperation = 2;
11'b11001011000: if(ALUOp>=2) assign ALUOperation = 6;
11'b10001010000: if(ALUOp>=2) assign ALUOperation = 0;
11'b10101010000: if(ALUOp>=2) assign ALUOperation = 1;
default:
if(ALUOp == 0) assign ALUOperation = 2;
else if(ALUOp >= 1) assign ALUOperation = 7;
endcase
end
endmodule
module ALU(ALUOperation, A, B, ALUResult, Zero);
input [63:0] A;
input [63:0] B;
input [3:0] ALUOperation;
output reg [63:0] ALUResult;
output Zero;
always @(A,B,ALUResult)begin
case(ALUOperation)
0:ALUResult <= A & B;
1:ALUResult <= A | B;
2:ALUResult <= A + B;
6:ALUResult <= A - B;
7:ALUResult <= B;
12:ALUResult <= ~(A | B);
default: ALUResult <= 0;
endcase
end
endmodule
Explanation / Answer
# Have done some modifications in code for behavioral model.
lab3cc(
input [1:0] ALUOp,
input [10:0] ALU_SEL //to mention the ALU selected value
input [10:0] OpcodeField,
input [63:0] A,
input [63:0] B,
output CarryOut //to carryout the flag
Output [63:0] // ALU specified bit output
output reg [63:0] ALUResult,
output Zero
);
wire [3:0] ALUOperation;
ALUControl first_unit(
A,B // ALU Inputs
ALU_Sel, //Selection of ALU Values
ALUControl first(ALUOp, OpcodeField, ALUOperation);
ALU second(ALUOperation, A, B, ALUResult, Zero);
endmodule
module ALUControl(ALUOp, OpcodeField, ALUOperation);
input [1:0] ALUOp;
input [10:0] OpcodeField;
output reg [3:0] ALUOperation;
reg[3:0] ALU_Result;
assign ALU_Out = ALU_Result; //ALU output
assign carryout = tmp[]; //carryout flag
always @(ALUOp,OpcodeField )
begin
case(OpcodeField)
11'b10001011000: if(ALUOp>=2) assign ALUOperation = 2;
11'b11001011000: if(ALUOp>=2) assign ALUOperation = 6;
11'b10001010000: if(ALUOp>=2) assign ALUOperation = 0;
11'b10101010000: if(ALUOp>=2) assign ALUOperation = 1;
default:
if(ALUOp == 0) assign ALUOperation = 2;
else if(ALUOp >= 1) assign ALUOperation = 7;
endcase
end
endmodule
module ALU(ALUOperation, A, B, ALUResult, Zero);
input [63:0] A;
input [63:0] B;
input [3:0] ALUOperation;
reg[3:0] ALU_Result;
assign ALU_Out = ALU_Result; //ALU output
assign carryout = tmp[]; //carryout flag
output reg [63:0] ALUResult;
wire[63:0] ALU_OUT;
wire CarryOut //for outputs
output Zero;
always @(A,B,ALUResult)begin
case(ALUOperation)
0:ALUResult <= A & B;
1:ALUResult <= A | B;
2:ALUResult <= A + B;
6:ALUResult <= A - B;
7:ALUResult <= B;
12:ALUResult <= ~(A | B);
default: ALUResult <= 0;
endcase
end
endmodule
Hope this helps you.All the best
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