Question 2: DFF Below are the DFF logic symbol and circuit diagram (from ic_diag

Question

Question 2: DFF Below are the DFF logic symbol and circuit diagram (from ic_diagrams.pdf) 14VDD 1CLR 1D 1CLK 1PRE 1Q 1Q PRESET reset D Q 13 2CLR Output Data Pin Q D 4 2CLK 2PRE 2Q 2Q Inverted Clock Output 8 GND[7 7474 FLOP Symbol: D Flip-flop Using the logic diagram of the DFF below to complete the DFF truth table. Clock a bar CLK 0 0 0 0 Notes The right half of the DFF logic diagram is exactly the SR FF. Take advantage of that fact. - The DFF chip we use in the lab will have two more inputs: Preset and Reset. Their functions wil be introduced during the lab The clock signal on the DFF chip will be a little more complicated than it is in the circuit above. In the chip, the clock will trigger the change in output Q only during a positive clock edge. A positive clock edge is when the clock signal changes from 0 to 1, while a negative clock edge is when the clock signal changes from 1 to 0

Explanation / Answer

D flip flop normally outputs what ever the input you give i.e., D only when the clock pulse changes. This acts only as a memory element which can store 1 bit of memory.

Let us assume the previous state of flip flop be Q=0 and Q'=1.

Let us represent the nand gates with numbers left most top one be nand-1, bottom one be nand-2, right most top be nand-3, bottom be nand-4.

This helps us constructing truth table.

Nand truth table:

A B O

0 0 1

0 1 1

1 0 1

1 1 0

case 1:clk=0 and D=0

now nand-1 has inputs 0,0 from clk and D respectiviley. So it gives output 1 ( check truth table mentioned above ) . For nand -2 has inputs 0,1 from clk and D' respectiviley. So it gives output 1. For Nand-3 it has inputs 1,1 from nand-1 and Q' respectively. So it outputs 0.  For Nand-4 it has inputs 1,0 from nand-2 and Q respectively. So it outputs 1. So finally Q=0, Q'=1 (which is the previous state)

case 2:clk=0 and D=1

now nand-1 has inputs 0,1 from clk and D respectiviley. So it gives output 1 . For nand -2 has inputs 0,0 from clk and D' respectiviley. So it gives output 1. For Nand-3 it has inputs 1,1 from nand-1 and Q' respectively. So it outputs 0.  For Nand-4 it has inputs 1,0 from nand-2 and Q respectively. So it outputs 1. So finally Q=0, Q'=1 (which is the previous state)

case 3:clk=1 and D=0

now nand-1 has inputs 1,0 from clk and D respectiviley. So it gives output 1 ( check truth table mentioned above ) . for nand -2 has inputs 1,1 from clk and D' respectiviley. So it gives output 0. For Nand-3 it has inputs 1,1 from nand-1 and Q' respectively. So it outputs 0.  For Nand-4 it has inputs 0,0 from nand-2 and Q respectively. So it outputs 1. So finally Q=0, Q'=1 (which is the data input you gave).

case 4:clk=1 and D=1

now nand-1 has inputs 1,1 from clk and D respectiviley. So it gives output 0 ( check truth table mentioned above ) . for nand -2 has inputs 1,0 from clk and D' respectiviley. So it gives output 1. For Nand-3 it has inputs 0,1 from nand-1 and Q' respectively. So it outputs 1.  For Nand-4 it has inputs 1,1 from nand-2 and Q respectively. So it outputs 0. So finally Q=1, Q'=0 (which is the data input you gave).

Hence truth table becomes:

Nand truth table:

CLK D Q Q'

0 0 0 1

0 1 0 1

1 0 0 0

1 1 1 1

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