1. (50 points) The following instructions are executed on the 5-stage MIPS pipel
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1. (50 points) The following instructions are executed on the 5-stage MIPS pipelined datapath add r5,r2, r1 lw r3, 4(r5) lw r2, 0(r2) or r3, r5, r: sw r3, 0(r5) (a) (20 points) List the data hazards in the above code. For each data hazard identified, clearly mark the source and the destination. For example you can say, there is a data hazard from instruction X to instruction Y on register Z. (b) (20 points) Assume there is no forwarding hardware implemented Draw the pipelined diagram, showing all the pipeline stalls necessary to ensure correct execution (c) (20 points) Assume the following forwarding hardware is added to the processor: EX-EX, MEM-EX, and MEM-MEM. Show the pipelined execution of the instructions and highlight relevant data forwarding paths. Stalls should be inserted only when a data hazard cannot be avoided with forwardingExplanation / Answer
answer
Stalling
Figure 6.45
What happen during stall?A nop instruction profits through the tube.
This nop begin in the EX stage (remember hazard is caught up in ID stage).
The nop is shaped by deasserting all nine manage signals - in essence an teaching that does not anything and saves no change.
Can be inserted by altering EX, MEM and WB control field to ID/EX pipeline list to 0s.Is a 1-cycle stall long enough?Yes - keep in mind that forwarding can grip data read hazards as long as present is one teaching in between the write plus the read.
For best presentation, the compiler be supposed to also try to avoid stall situation, if possible.
Figure 6.46
Control Hazards
Control hazards are comparatively simple to appreciate and they occur a large amount less frequently than data hazards, but present is nothing as effectual against control hazards as forward is for data hazards
Three solution to control hazard:
Stall(nicknamed bubble) - silence before ongoing on.Not a good answer - can result in significant hold up. Predict- forecast that branch will be unsuccessful.
If succeed, result (on execution time) is similar as a stall. If branch fails, no presentation loss.Delayed decision- do amazing else while wait for choice.
tube with stalling (figure 6.4).
Assumes result is made in second stage. Pipeline with forecast (figure 6.5): Predictions Can be more sophisticated concerning forecast.
Example: could predict so as to a branch that jumps to an previous address will be in use (assume it's a loop).Branch maritalot Taken plan.
Continues execution as if bough will fail. If branch is in use, instructions in tube are surplus. If branches are untaken semi the time, this optimization halve the cost of control hazard.
How to implement?
Change manage values to 0s, now as for load-use hazard. Must alter in all registers with orders fetched after bough instruction (IF, ID, EX).
plummeting the Delay of Branches Goal:
move branch carrying out earlier in pipeline, so fewer orders to discard if prediction is wrong.
Many MIPS implementations shift choice to ID stage.Branch adder move from MEM stage to ID stage.Branch decision is completed by using xor and then or on two register
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