Describe some of the current problems with the computer architecture these days.
ID: 3736530 • Letter: D
Question
Describe some of the current problems with the computer architecture these days. You can search online for the current issues we have with the computer architecture, choose one issue and write about it and be specific about what the problem is and include some recommendations on how to solve it. You can do this by searching online to see what scientist are doing right now to deal with this problem.Please type it not writing it. Describe some of the current problems with the computer architecture these days. You can search online for the current issues we have with the computer architecture, choose one issue and write about it and be specific about what the problem is and include some recommendations on how to solve it. You can do this by searching online to see what scientist are doing right now to deal with this problem.
Please type it not writing it.
Please type it not writing it.
Explanation / Answer
Compuiter architecture is described as the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation. Computer architecture is the practical art of defining the structure and relationship of the subcomponents of a computer.
I would choose power consumption as the major problem in the Compuiter architecture now a days. Demand for the computing industry is fast computation with minimum power consumption and smaller processing element (PE) size. We need to minimize power consumption to save power, specifically for the PE but the purpose is not to save power but to avoid thermal problems. Reducing power consumption has become a major challenge in the design and operation of today’s computer systems. Improvements in semiconductor technology make it possible to incorporate millions of transistors on a very small die and to clock them at very high speeds. Architecture and system software technology also offer tremendous performance improvements by exploiting parallelism in a variety of forms. While the demand for even more powerful computers would be hindered by the physics of computational systems such as the limits on voltage and switching speed, a more critical and imminent obstacle is the power consumption and the corresponding thermal and reliability concerns. This applies not only to low-end portable systems but also to high-end system designs. Since portable systems such as laptop computers and cell phones draw power from batteries, reducing power consumption to extend their operating times is one of the most critical product specifications. This is also a challenge for high-end system designers because high power consumption raises temperature, which deteriorates performance and reliability.
Power efficiency is another important measurement in modern computers. A higher power efficiency can often be traded for lower speed or higher cost. The typical measurement when referring to power consumption in computer architecture is MIPS/W (millions of instructions per second per watt).
Modern circuits have less power required per transistor as the number of transistors per chip grows. This is because each transistor that is put in a new chip requires its own power supply and requires new pathways to be built to power it. However the number of transistors per chip is starting to increase at a slower rate. Therefore, power efficiency is starting to become as important, if not more important than fitting more and more transistors into a single chip. In the world of embedded computers, power efficiency has long been an important goal next to throughput and latency. As the power problem has become prominent for computer architects, many ideas have been proposed for managing power and energy issues through architectural techniques. In order to compare these many ideas, quantitative techniques for architecture-level power modeling have become very important.
Power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized.
Recent advances in multi-core and multi-threading technologies have seen a great growth in CPU processing power caused by the progression of smaller transistors in fabrication technologies. This reduction in transistor size permits the integration of billions of transistors on a single chip to enhance the performance of System-on-Chip (SoC)-based applications. As this increase in core count continues to grow rapidly, communication between them becomes an essential requirement for future SoC design. The on-chip interconnect, which was primarily used to establish this communication, was the traditional bus-based system. However, bus-based architectures’ inability to cope and sustain this advancement in technology creates a performance bottleneck in the system. Therefore, the Network-on-Chip (NoC) paradigm has emerged as the integral backbone of emerging computer systems, thus shifting the focus of the development of technology to the enhancement of network performance. Power-hungry components such as the input buffers and crossbars limit designers from maximising the capabilities of these systems. Continuous switching of activities results in high dynamic and leakage power consumption, thus causing a surge in the amount of power consumed on the chip.
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