MIPS Inst/Cyclel 1 2 ID 6 4 MEM WB EX ID 5 EX ID IF IF MEM WB EX pipeline suppor

Question

MIPS

Inst/Cyclel 1 2 ID 6 4 MEM WB EX ID 5 EX ID IF IF MEM WB EX pipeline support MEM |WB Table 3 Instruction Execution with There are, though, situations in the pipelining when the next instruction cannot execute in the following clock cycle. These events are called Hazards and there are three different types [1] A. Structural Hazard. When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute [1] B. Data Hazard or Pipeline Data Hazard. When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available [1] C. Control Hazard or Branch Hazard. When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected [1]

Explanation / Answer

1.

Ignore all hazards:

2.ignoring all possible hazards we are doing here $t5 initial value we are assuming here zero

LW $t0,0($t3) --->t0=2   

Sub $t1,$t0,$t2 => $t1=2+8=10

add $t3,$t3,$t1 =>$t3=2+5=7

addi $t4,$t4,8 =>$t4=4+8 =12

sub $t5,$t5,$t4 => $t5=0+4=4

3.

4.

in the above table, we observed that there are 6 NOP operations that mean 6 stalls or bubbles. we are wasting that much time for calculating the actual values. These NOP operations came into picture because of data dependency between previous to the next instruction. here basically data hazards are here and also only single memory so mem and id stage came in the same clock cycle that will leads to strctural hazard.

here we removing NOP operation instead of NOP instruction we are issuiing the instruction like data dependency not there. observe 1st instruction lw and 4th instruction addi there is no data dependency...etc below code is the instrcution reordered.

we got here only 3 NOP instructions.

5. in the above section we are reordered the code now we are adding forwarding feature to the pipleline that leads to removal of NOP Instruction in between instructions.structual hazard can be removed by divding the clock cycle into two parts in the first half cycle it will read the data in the second half of the cycle it wiil write the data into the memory.

ZERO NOP instructions. only forwarding some times leads to stalls in between the instructions. we can remove that type stalls by code reordering method.

instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LW $t0,0($t3) IF ID EX MEM WB Sub $t1,$t0,$t2    IF ID EX MEM WB add $t3,$t3,$t1 IF ID EX MEM WB addi $t4,$t4,8    IF ID EX MEM WB sub $t5,$t5,$t4   IF ID EX MEM WB

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