PLEASE USE ARM, NOT MIPS. 2. Hazard Consider the following sequence of instructi

Question

PLEASE USE ARM, NOT MIPS.

2. Hazard Consider the following sequence of instructions LDR R1, LDR R2, ADD R3, [R2, #0] [R3, #0] R1, R2 For each of the question below, assume the stalls have to be handled by the compiler by inserting NOP instructions (a) Assume there is no forwarding in this pipelined processor. Write the code with the proper NOP instructions added (b) Assume there is forwarding. Write the code with proper NOP instructions added (c) Assume there is only EX-EX forwarding only. Write the code wiith proper NOP nstructions added

Explanation / Answer

(a) LDR R1, [R2, #0]
LDR R2, [R3, #0]
NOP
NOP
NOP
ADD R3,R1,R2

Explanation: Since there is no forwarding the result of Load instruction will get stored in R2 after WB step of Instruction second. The add instruction needs the data from R2 in the ID stage, there is a gap of three stages between them. So there must be three NOPs.

(b)LDR R1, [R2, #0]
LDR R2, [R3, #0]
NOP
ADD R3,R1,R2

Explanation: We have just put one NOP here because as soon as the MEM stage of load instruction gets the data from memory, we can forward that for EX stage of ADD instruction.

(c)LDR R1, [R2, #0]
LDR R2, [R3, #0]
NOP
NOP
NOP
ADD R3,R1,R2

Explanation: There is no use of EX-EX forwarding here because the dependency is on the load instruction which has to do the memory access.

Related Questions

Navigate

• Browse (All)
• Browse P
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.