20. Which of the following interrupts cannot be ignored by the CPU? A. Serial B.
ID: 3724891 • Letter: 2
Question
20. Which of the following interrupts cannot be ignored by the CPU? A. Serial B. Reset C. External D. Timers 21. A subroutine called from within another subroutine is referred to as a A. caged subroutine B. nested subroutine C. stacked subroutine D. secondary subroutine 22. Executing the instruction MOV P1, A cause's A the data in A to be sent out port P1 for a brief timer interval B. the value contained in A to be sent out port P1 and latched C. register A to be set to the value contained in port P1 D. the value in port P1 to be set to the constant A 23. What is the final result in the accumulator after the execution of the following program segment? MOV A, #55H ANL A, #0FH CPL A A. 55H B. FAH C. AAH D. 35H 24. Which of the following is always bi-directional? A The enable line B. The data bus C. The address bus D. The control bus 25. What is the final result of the P1 port after the execution of the following program segment? MOV A, #0FFH MOV P1, A A. 8BH B. FFH C. 7BH D. 7DHExplanation / Answer
Solution:
The first four subparts have been answered as per Chegg guidelines, please repost others.
20)
Timer and Reset are the ones which can not be ignored by the CPU.
21)
The subroutine in another subroutine is called as the nested subroutine.
22)
MOV P1,A ;send it to port 1
so D option is correct here
23)
ANL
Bitwise AND
CPL
Function: Complement Register
. If the operand is the Accumulator then all the bits in the Accumulator will be reversed
MOV --> 55H 01010101
ANL --> 0FH 00001111
------------------------------------
00000101
complement======>11111010 [FAH]
B is correct.
24)
The data bus, B is correct
the data bus is bidirectional because it transfers information between peripheral devices and memory register.but, the address bus is unidirectional because it simply receives information
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