P4. (10 pts) Use with-select and when statements to write a complete VHDL code t
ID: 3724786 • Letter: P
Question
P4. (10 pts) Use with-select and when statements to write a complete VHDL code to describe the circuit represented by the following truth table. Your VHDL code should not describe the Boolean equation of the circuit. Hint: recall we discussed a similar problem in class. Instead of using BIT or BIT_VECTOR, you should use STD_LOGIC or STD LOGIC_VECTOR. 0 0 0 0 0 0 0 0 P5. (10 pts) Use structural modeling technique to write a complete VHDL code for the circuit described by logic function Y= AC+ A'B + ABC, by using a 8:1 multiplexer. Your VHDL code should be in text format (not image, not screen capture) so that we can copy and paste it into Active-HDL software to compile it.Explanation / Answer
P4.
---------VHDL CODE FOR GIVEN TRUTH TABLE----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Booleanexpression is
port( A : in std_logic_vector(2 downto 0);---a=A(2),B=A(1),C=A(0);
Y: out std_logic); --output Y
end Booleanexpression;
architecture truthtable of Booleanexpression is
begin
with A select Y<=
'0' when "000",
'1' when "001",
'1' when "010",
'1' when "011",
'0' when "100",
'0' when "101",
'1' when "110",
'0' when "111",
'0' when others;
end truthtable;
(The above code is executed and error free, If you have any query leave a comment, Thank you)
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