7. Given a DRAM memory chip that is 1M x 1 that is organized into 1024 rows and

Question

7. Given a DRAM memory chip that is 1M x 1 that is organized into 1024 rows and may be refreshed one row at a time. Every cell in the DRAM must be refreshed at least once every four milliseconds. Assume that the refresh is done on a periodic basis. Answer the following: A) What is the maximum time period between successive refresh requests? B) How long is the refresh address? C) If the read access time is 40 nsec and the time it takes to refresh a single row takes 80nsec what percent of the total time available is taken up by memory refresh cycles?

Explanation / Answer

Given, a DRAM of 1MB x 1 organised into 1024 rows, where every row must be refreshed every 4 millisecond.

A.) The Maximum time period between successive refresh request(Refresh Cycle Interval)= Refresh Time/Number of Rows

=> 4ms/1024=3.9 us

b.) How long the refresh address: 4ms

c)

Read access time=40nsec

time to refresh a single row= 80nsec

time require for refresh= 80 nces+40 nsec=120 nsec

refresh interval= 3.9 us= 3900 nsec(As calculated in question A)

refresh overlod= time require for a refresh/ refresh interval= 120/3900=0.0307

So 3.07 % of total time is taken up by memory refresh cycles

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