Build a 4 bit ALU, stringing together four 1 bit ALU\'s (the last one with overf

Question

Build a 4 bit ALU, stringing together four 1 bit ALU's (the last one with overflow detection and SET output), that does addition, subtraction, and, or, and set on less than. Use good hierarchal design and keep the Verilog code as elementary as possible. Create a separate module for the instance of the 4-bit ALU.

Base your answer off of the following ALU definition:

module ALU (ALUctl, A, B, ALUOut, Zero);

   input [2:0] ALUctl;
   input [3:0] A,B;
   output reg [3:0] ALUOut;
   output Zero;
   assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0;

   always @(ALUctl, A, B) //reevaluate if these change

   case (ALUctl)
           0: ALUOut <= A & B;
           1: ALUOut <= A | B;
           2: ALUOut <= A + B;
           6: ALUOut <= A - B;
           7: ALUOut <= A < B ? 1:0;
     default: ALUOut <= 0;
   endcase

endmodule

Explanation / Answer

module ALU_4bit (ALUctl, A, B, ALUOut, Zero);

input [2:0] ALUctl;
input [3:0] A,B;
output [3:0] ALUOut;
output Zero, Overflow;

reg [3:0] reg1;

ALU_4bit DUT0 (.A(A[0]), .B(B[0]), .ALUctl(ALUctl), .ALUOut(ALUOut[0]), .Zero(reg1[0]) );

ALU_4bit DUT1 (.A(A[1]), .B(B[1]), .ALUctl(ALUctl), .ALUOut(ALUOut[1]), .Zero(reg1[1]) );

ALU_4bit DUT2 (.A(A[2]), .B(B[2]), .ALUctl(ALUctl), .ALUOut(ALUOut[2]), .Zero(reg1[2]) );

ALU_4bit DUT3 (.A(A[3]), .B(B[3]), .ALUctl(ALUctl), .ALUOut(ALUOut[3]), .Zero(reg1[3]) );

assign Zero = &reg1;

assign Overflow = (ALUctl[1:0] == 2'b10) ? (ALUOut[3] ^ ALUOut[2]) : 1'b0;

endmodule

module ALU_1bit (ALUctl, A, B, ALUOut, Zero);

input [2:0] ALUctl;
input A, B;
output reg ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0;

always @(*) //reevaluate if these change

case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1'b1 : 1'b0;
default: ALUOut <= 0;
endcase

endmodule

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