Question 1 (Memory and Behavioral VHDL Coding) Consider a 1-MByte cache with 4-w

Question

Question 1 (Memory and Behavioral VHDL Coding)
Consider a 1-MByte cache with 4-word cachelines (a cacheline is also
known as a cache block, each word is 4-Bytes). The address is 64-bits
wide.
(a) Assume the cache is direct-mapped. Fill in the table below to specify
the size of each address field.
(b)Assume the cache is 4-way set-associative. Fill in the table below to
specify the size of each address field.
(c) What is the overhead and actual size of the direct-mapped cache?
What is the overhead and actual size of the 4-way set-associative
cache? Does the structure change the overhead in terms of number
of memory bits? Consider 1-valid bit per-cacheline.
(d) Write VHDL code 1-KByte cache (RAM)

Explanation / Answer

Solution:

Note: a and b is solved, please repost c and d.

1)

a)

Cache size = 1 MB

cache line size = 4-word = 2^2 * 2^2 bytes

2^4 bytes

word size = 4 bytes

Number of cache lines = cache size/ line size = 2^20/2^4 = 2^16

which means 16 bits are required top address the cache lines

The memory is 64 bit wide this means

b)

In case of 4-way set associative

number of sets = number of cache lines/ P-way = 2^16/2^2 = 2^14

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