Use the following code fragment: ;load R1 from address 8+R2 R1-R1+1 Loop: LW R1e

Question

Use the following code fragment: ;load R1 from address 8+R2 R1-R1+1 Loop: LW R1e(R2) R1 at address 8+R2 SW R1, (R2 ADDI R2R24 SUB R4R3 R2 R2-R2+4 R4-R3-R2 ,branch to Loop if R41-e Assume that the initial value of R3 is R2 396 Further assume that the branch addresses are calculated during the ID phase and branch prediction is handled as designated in the tables 2.1 of the appendix. a. Data hazards are caused by data dependences in the code. List all of the data dependences in the code above. Record the register, source instruction, and destination instruction; for example, there is a data dependency for register R1 from the LW to the ADDI b. Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the register file. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to execute? c. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Assume that the branch is handled by predicting it as not taken. If all memory references take 1 cycle, how many cycles does this loop take to execute? d. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Assume that the branch is handled by predicting it as taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?

Explanation / Answer

Answer is as follows :

According to Chegg Guidelines, we are allowed to solve only first three parts, so please repost others.

a) Data dependencies :

b) Pipeline without forwarding and byPassing :

Total Cycles = 19

c) With Forwarding withou branch prediction :

Total Cycles = 12

Signals :

FI = Fetch Instruction

ID = instruction Decoding

EX = Execution

MEM = Memory Read/Write

WB = Register Write

* represent stalls.

if there is any query please ask in comments...

Cycles-> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lwr1,0(r2) IF ID EX MEM WB addi r1,r1,1 IF * * ID EX MEM WB sw r1,0(r2) IF * * ID EX MEM WB addi r2,r2,4 IF * * ID EX MEM WB sub r4,r3,r2 IF * ID EX MEM WB bnez r4,loop IF * * ID EX MEM WB

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