1. Write behavioral VHDL code that implements the state machine that you designe
ID: 3710608 • Letter: 1
Question
1. Write behavioral VHDL code that implements the state machine that you designed in the previous module. Use a case statement to represent the state table as illustrated in the figure below. Use two processes – one for the combinational logic and one for the state register. Add an asynchronous reset input. 1 entity SM17_2 is 2 port(X,CLK: in bit; 3 Z:out bit); 4 end SM17_2; 5 architecture Table of SM17_2 is 6 signal State, Nextstate: integer range 0 to 6:= 0; 7 begin 8 process(State,X) --Combinational Cicuit 9 begin 10 case State is 11 when 0=> 12 if X='0' then Z<='1'; Nextstate<=1; 13 else Z<='0'; Nextstate<=2; end if; 14 when 1=> 15 if X='0' then Z<='1'; Nextstate<=3 16 else Z<='0'; Nextstate<=4; end if; 17 when 2=> 18 if X='0' then Z<='0'; Nextstate<=4 19 else Z<='1'; Nextstate<=4; end if; 20 when 3=> 21 if X='0' then Z<='0'; Nextstate<=5 22 else Z<='1'; Nextstate<=5; end if; 23 when 4=> 24 if X='0' then Z<='1'; Nextstate<=5 25 else Z<='0'; Nextstate<=6; end if; 26 when 5=> 27 if X='0' then Z<='0'; Nextstate<=0 28 else Z<='1'; Nextstate<=0; end if; 29 when 6=> 30 Z<='1'; Nextstate<=0; 31 end case; 32 end process; 33 process (CLK) --State Register 34 begin 35 if CLK'event and CLK='1' then --rising edge of clock 36 State<=Nextstate; 37 end if; 38 end process; 39 end table; Submit your VHDL
Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SM17_2 is
port(
X, CLK, RST : in bit;
Z : out bit
);
end SM17_2;
architecture Behavioural of SM17_2 is
type state_type is (S0, S1, S2, S3, S4, S5, S6);
signal State, Nextstate : state_type;
begin
process(State,X) --Combinational Cicuit
begin
case State is
when S0 =>
if (X = '0') then
Z <= '1'; Nextstate <= S1;
else
Z <= '0'; Nextstate <= S2;
end if;
when S1 =>
if (X='0') then
Z <= '1'; Nextstate <= S3;
else
Z <= '0'; Nextstate <= S4;
end if;
when S2 =>
if (X = '0') then
Z <= '0'; Nextstate <= S4;
else
Z <= '1'; Nextstate <= S4;
end if;
when S3 =>
if (X = '0') then
Z <= '0'; Nextstate <= S5;
else
Z <= '1'; Nextstate <= S5;
end if;
when S4 =>
if (X = '0') then
Z <= '1'; Nextstate <= S5;
else
Z <= '0'; Nextstate <= S6;
end if;
when S5 =>
if (X = '0') then
Z <= '0'; Nextstate <= S0;
else
Z <= '1'; Nextstate <= S0;
end if;
when S6 =>
Z <= '1'; Nextstate <= S0;
end case;
end process;
process (CLK, RST)
begin
if (RST = '1') then -- asynchronous Reset
State <= S0;
elsif (CLK'event and CLK = '1') then --rising edge of clock
State <= Nextstate;
end if;
end process;
end Behavioural;
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